Manuel D’UtilisationTable des matièresList of Sections3Table of Contents5General Description5Section 2. Memory Map5Section 3. Random-Access Memory (RAM)6Section 4. Read-Only Memory (ROM)6Section 5. Configuration Register (CONFIG)6Section 6. Central Processor Unit (CPU)6Section 7. System Integration Module (SIM)7Section 8. Clock Generator Module (CGM)8Section 9. Universal Serial Bus Module (USB)9Section 10. Monitor ROM (MON)10Section 11. Timer Interface Module (TIM)10Section 12. I/O Ports11Section 13. Computer Operating Properly (COP)12Section 14. External Interrupt (IRQ)12Section 15. Keyboard Interrupt Module (KBI)13Section 16. Break Module (BREAK)14Section 17. Preliminary Electrical Specifications14Section 18. Mechanical Specifications15List of Figures17List of Tables21Section 1. General Description231.1 Contents231.2 Introduction241.3 Features241.4 MCU Block Diagram261.5 Pin Assignments281.5.1 Quad Flat Pack (QFP) Package281.5.2 Power Supply Pins (VDDA, VSSA, VDD1, VSS1, VDD2, and VSS2)291.5.3 Oscillator Pins (OSC1 and OSC2)301.5.4 External Reset Pin (RST)301.5.5 External Interrupt Pin (IRQ1/VPP)301.5.6 USB Data Pins (DPLUS0-DPLUS4 and DMINUS0-DMINUS4)301.5.7 Voltage Regulator Out (REGOUT)301.5.8 Port A Input/Output (I/O) Pins (PTA7-PTA0)311.5.9 Port B I/O Pins (PTB7-PTB0)311.5.10 Port C I/O Pins (PTC4-PTC0)311.5.11 Port D I/O Pins (PTD7/KBD7-PTD0/KBD0)311.5.12 Port E I/O Pins (PTE4, PTE3/KBE3, PTE2/KBE2/TCH1, PTE1/KBE1/TCH0, PTE0/KBE0/TCLK)311.5.13 Port F I/O Pins (PTF7/KBF7-PTF0/KBF0)32Section 2. Memory Map332.1 Contents332.2 Introduction332.3 I/O Section352.4 Monitor ROM43Section 3. Random-Access Memory (RAM)453.1 Contents453.2 Introduction453.3 Functional Description45Section 4. Read-Only Memory (ROM)474.1 Contents474.2 Introduction474.3 Functional Description47Section 5. Configuration Register (CONFIG)495.1 Contents495.2 Introduction495.3 Functional Description49Section 6. Central Processor Unit (CPU)516.1 Contents516.2 Introduction516.3 Features526.4 CPU Registers526.4.1 Accumulator (A)536.4.2 Index Register (H:X)546.4.3 Stack Pointer (SP)556.4.4 Program Counter (PC)566.4.5 Condition Code Register (CCR)576.5 Arithmetic/Logic Unit (ALU)59Section 7. System Integration Module (SIM)617.1 Contents617.2 Introduction627.3 SIM Bus Clock Control and Generation657.3.1 Bus Timing657.3.2 Clock Start-Up from POR667.3.3 Clocks in Stop Mode and Wait Mode667.4 Reset and System Initialization667.4.1 External Pin Reset677.4.2 Active Resets from Internal Sources677.4.2.1 Power-On Reset687.4.2.2 Computer Operating Properly (COP) Reset697.4.2.3 Illegal Opcode Reset707.4.2.4 Illegal Address Reset707.4.2.5 Universal Serial Bus Reset707.5 SIM Counter717.5.1 SIM Counter During Power-On Reset717.5.2 SIM Counter During Stop Mode Recovery717.5.3 SIM Counter and Reset States717.6 Exception Control727.6.1 Interrupts727.6.1.1 Hardware Interrupts747.6.1.2 SWI Instruction767.6.2 Interrupt Status Registers767.6.2.1 Interrupt Status Register 1777.6.2.2 Interrupt Status Register 2787.6.2.3 Interrupt Status Register 3787.6.3 Reset797.6.4 Break Interrupts797.6.5 Status Flag Protection in Break Mode797.7 Low-Power Modes797.7.1 Wait Mode807.7.2 Stop Mode817.8 SIM Registers837.8.1 Break Status Register (BSR)837.8.2 Reset Status Register (RSR)847.8.3 Break Flag Control Register (BFCR)85Section 8. Clock Generator Module (CGM)878.1 Contents878.2 Introduction888.3 Features898.4 Functional Description898.4.1 Crystal Oscillator Circuit918.4.2 Phase-Locked Loop Circuit (PLL)918.4.3 PLL Circuits918.4.4 Acquisition and Tracking Modes938.4.5 Manual and Automatic PLL Bandwidth Modes938.4.6 Programming the PLL948.4.7 Special Programming Exceptions958.4.8 Base Clock Selector Circuit968.4.9 CGM External Connections968.5 I/O Signals988.5.1 Crystal Amplifier Input Pin (OSC1)988.5.2 Crystal Amplifier Output Pin (OSC2)988.5.3 External Filter Capacitor Pin (CGMXFC)988.5.4 PLL Analog Power Pin (VDDA)988.5.5 PLL Analog Ground Pin (VSSA)988.5.6 Buffered Crystal Clock Output (CGMVOUT)998.5.7 CGMVSEL998.5.8 Oscillator Enable Signal (SIMOSCEN)998.5.9 Crystal Output Frequency Signal (CGMXCLK)998.5.10 CGM Base Clock Output (CGMOUT)998.5.11 CGM CPU Interrupt (CGMINT)998.6 CGM Registers1008.6.1 PLL Control Register (PCTL)1028.6.2 PLL Bandwidth Control Register (PBWC)1048.6.3 PLL Multiplier Select Registers (PMSH:PMSL)1058.6.4 PLL Reference Divider Select Register (PRDS)1068.7 Interrupts1078.8 Special Modes1078.8.1 Wait Mode1078.8.2 CGM During Break Interrupts1088.9 Acquisition/Lock Time Specifications1088.9.1 Acquisition/Lock Time Definitions1088.9.2 Parametric Influences on Reaction Time1098.9.3 Choosing a Filter Capacitor1118.9.4 Reaction Time Calculation111Section 9. Universal Serial Bus Module (USB)1139.1 Contents1139.2 Features1149.3 Overview1159.4 I/O Register Description of the HUB function1169.4.1 USB HUB Root Port Control Register (HRPCR)1209.4.2 USB HUB Downstream Port Control Register (HDP1CR-HDP4CR)1219.4.3 USB SIE Timing Interrupt Register (SIETIR)1239.4.4 USB SIE Timing Status Register (SIETSR)1259.4.5 USB HUB Address Register (HADDR)1279.4.6 USB HUB Interrupt Register 0 (HIR0)1289.4.7 USB HUB Control Register 0 (HCR0)1299.4.8 USB HUB Endpoint1 Control & Data Register (HCDR)1319.4.9 USB HUB Status Register (HSR)1329.4.10 USB HUB Endpoint 0 Data Registers 0-7 (HE0D0-HE0D7)1349.5 I/O Register Description of the Embedded Device Function1349.5.1 USB Embedded Device Address Register (DADDR)1389.5.2 USB Embedded Device Interrupt Register 0 (DIR0)1389.5.3 USB Embedded Device Interrupt Register 1 (DIR1)1409.5.4 USB Embedded Device Control Register 0 (DCR0)1419.5.5 USB Embedded Device Control Register 1 (DCR1)1439.5.6 USB Embedded Device Status Register (DSR)1449.5.7 USB Embedded Device Control Register 2 (DCR2)1469.5.8 USB Embedded Device Endpoint 0 Data Registers (DE0D0-DE0D7)1479.5.9 USB Embedded Device Endpoint 1/2 Data Registers (DE1D0-DE1D7)148Section 10. Monitor ROM (MON)14910.1 Contents14910.2 Introduction14910.3 Features15010.4 Functional Description15010.4.1 Entering Monitor Mode15210.4.2 Data Format15410.4.3 Echoing15410.4.4 Break Signal15510.4.5 Commands15510.4.6 Baud Rate159Section 11. Timer Interface Module (TIM)16111.1 Contents16111.2 Introduction16211.3 Features16211.4 Functional Description16311.4.1 TIM Counter Prescaler16511.4.2 Input Capture16511.4.3 Output Compare16511.4.3.1 Unbuffered Output Compare16611.4.3.2 Buffered Output Compare16611.4.4 Pulse Width Modulation (PWM)16711.4.4.1 Unbuffered PWM Signal Generation16811.4.4.2 Buffered PWM Signal Generation16911.4.4.3 PWM Initialization17011.5 Interrupts17111.6 Wait Mode17111.7 TIM During Break Interrupts17211.8 I/O Signals17211.8.1 TIM Clock Pin (PTE0/TCLK)17211.8.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1)17311.9 I/O Registers17311.9.1 TIM Status and Control Register (TSC)17311.9.2 TIM Counter Registers (TCNTH:TCNTL)17511.9.3 TIM Counter Modulo Registers (TMODH:TMODL)17611.9.4 TIM Channel Status and Control Registers (TSC0:TSC1)17711.9.5 TIM Channel Registers (TCH0H/L-TCH1H/L)181Section 12. I/O Ports18312.1 Contents18312.2 Introduction18412.3 Port A18612.3.1 Port A Data Register (PTA)18612.3.2 Data Direction Register A (DDRA)18612.4 Port B18812.4.1 Port B Data Register (PTB)18812.4.2 Data Direction Register B (DDRB)18912.5 Port C19012.5.1 Port C Data Register (PTC)19012.5.2 Data Direction Register C (DDRC)19112.6 Port D19212.6.1 Port D Data Register (PTD)19312.6.2 Data Direction Register D (DDRD)19312.7 Port E19512.7.1 Port E Data Register (PTE)19512.7.2 Data Direction Register E (DDRE)19612.7.3 Port-E Optical Interface Enable Register19812.8 Port F20212.8.1 Port F Data Register (PTF)20212.8.2 Data Direction Register F (DDRF)20312.9 Port Options20412.9.1 Port Option Control Register (POC)204Section 13. Computer Operating Properly (COP)20713.1 Contents20713.2 Introduction20713.3 Functional Description20813.4 I/O Signals20913.4.1 CGMXCLK20913.4.2 COPCTL Write20913.4.3 Power-On Reset21013.4.4 Internal Reset21013.4.5 Reset Vector Fetch21013.4.6 COPD (COP Disable)21013.4.7 COPRS (COP Rate Select)21013.5 COP Control Register (COPCTL)21113.6 Interrupts21113.7 Monitor Mode21113.8 Low-Power Modes21213.8.1 Wait Mode21213.8.2 Stop Mode21213.9 COP Module During Break Mode212Section 14. External Interrupt (IRQ)21314.1 Contents21314.2 Introduction21314.3 Features21314.4 Functional Description21414.4.1 IRQ1/Vpp Pin21514.5 IRQ Module During Break Interrupts21714.6 IRQ Status and Control Register (ISCR)217Section 15. Keyboard Interrupt Module (KBI)21915.1 Contents21915.2 Introduction22015.3 Features22015.4 Port-D Keyboard Interrupt Block Diagram22215.4.1 Port-D Keyboard Interrupt Functional Description22315.4.2 Port-D Keyboard Initialization22415.4.3 Port-D Keyboard Interrupt Registers22515.4.3.1 Port-D Keyboard Status and Control Register:22515.4.3.2 Port-D Keyboard Interrupt Enable Register22615.5 Port-E Keyboard Interrupt Block Diagram22815.5.1 Port-E Keyboard Interrupt Functional Description22915.5.2 Port-E Keyboard Initialization23015.5.3 Port-E Keyboard Interrupt Registers23115.5.3.1 Port-E Keyboard Status and Control Register23115.5.3.2 Port-E Keyboard Interrupt Enable Register23215.6 Port-F Keyboard Interrupt Block Diagram23415.6.1 Port-F Keyboard Interrupt Functional Description23515.6.2 Port-F Keyboard Initialization23615.6.3 Port-F Keyboard Interrupt Registers23715.6.3.1 Port-F Keyboard Status and Control Register23715.6.3.2 Port-F Keyboard Interrupt Enable Register23815.6.3.3 Port-F Pull-up Enable Register23915.7 Wait Mode23915.8 Stop Mode23915.9 Keyboard Module During Break Interrupts239Section 16. Break Module (BREAK)24116.1 Contents24116.2 Introduction24116.3 Features24216.4 Functional Description24216.4.1 Flag Protection During Break Interrupts24416.4.2 CPU During Break Interrupts24416.4.3 TIM During Break Interrupts24416.4.4 COP During Break Interrupts24416.5 Break Module Registers24416.5.1 Break Status and Control Register (BRKSCR)24516.5.2 Break Address Registers (BRKH and BRKL)24516.6 Low-Power Modes24616.6.1 Wait Mode24616.6.2 Stop Mode246Section 17. Preliminary Electrical Specifications24717.1 Contents24717.2 Introduction24717.3 Absolute Maximum Ratings24817.4 Functional Operating Range24917.5 Thermal Characteristics24917.6 DC Electrical Characteristics25017.7 Control Timing25117.8 Oscillator Characteristics25117.9 USB DC Electrical Characteristics25217.10 USB Low Speed Source Electrical Characteristics25317.11 USB High Speed Source Electrical Characteristics25417.12 HUB Repeater Electrical Characteristics25517.13 USB Signaling Levels25617.14 TImer Interface Module Characteristics25617.15 Clock Generation Module Characteristics25717.15.1 CGM Component Specifications25717.15.2 CGM Electrical Specifications25717.15.3 Acquisition/Lock Time Specifications258Section 18. Mechanical Specifications25918.1 Contents25918.2 Introduction25918.3 Plastic Quad Flat Pack (QFP)260Taille: 2,5 MoPages: 262Language: EnglishOuvrir le manuel