Data Sheet (KITMMA9550LEVM)Table of ContentsXtrinsic MMA955xL Intelligent Motion-Sensing Platform1Contents31 Variations of MMA955xL Device42 Typical Applications63 General Description73.1 Functional Overview73.2 Packaging Information83.2.1 Package diagrams83.2.2 Sensing Direction and Output Response93.2.3 Pin Functions93.3 Pin Function Descriptions103.4 System Connections103.4.1 Power Sequencing103.4.2 Layout Recommendations103.4.3 MMA955xL Platform as an Intelligent Slave113.4.4 MMA955xL Platform as a Sensor Hub134 Mechanical and Electrical Specifications144.1 Definitions144.2 Pin Groups144.3 Absolute Maximum Ratings144.4 Operating Conditions154.5 Electrostatic Discharge (ESD) and Latch-up Protection Characteristics154.6 General DC Characteristics154.7 Supply Current Characteristics164.8 Accelerometer Transducer Mechanical Characteristics164.9 ADC Characteristics164.10 ADC Sample Rates174.11 AC Electrical Characteristics184.12 General Timing Control184.13 I2C Timing194.13.1 Slave I2C194.13.2 Master I2C Timing194.14 Slave SPI Timing204.15 Flash Parameters215 Package Information225.1 Footprint and pattern information225.2 Marking235.3 Tape and reel information246 Revision History25Size: 338 KBPages: 26Language: EnglishOpen manual
User Manual (KITMMA9550LEVM)Table of ContentsMMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual1Chapter 1 About This Document151.1 Overview151.1.1 Purpose151.1.2 Audience151.2 Terms and acronyms151.3 Conventions171.4 Register figure conventions181.5 References19Chapter 2 Introduction212.1 Hardware features222.2 Software features222.3 Typical applications23Chapter 3 Pins and Connections243.1 Package pinout243.1.1 Pin functions253.1.2 Sensing direction and output response263.2 Pin descriptions273.2.1 VDD and VSS273.2.2 VDDA and VSSA273.2.3 RESETB273.2.4 Slave I2C: SDA0 and SCL0273.2.5 Master I2C: SDA1 and SCL1273.2.6 Analog-to-digital conversion: AN0, AN1283.2.7 Rapid General-Purpose I/O: RGPIO[9:0]283.2.8 Interrupts: INT283.2.9 Debug/mode control: BKGD/MS283.2.10 Timer: PDB_A and PDB_B293.2.11 Slave SPI interface: SCLK, SDI, SDO and SSB293.3 System connections303.3.1 Platform as an intelligent slave303.3.2 Platform as a sensor hub313.3.3 Power313.3.4 RESETB pin323.3.5 Background / mode select (BKGD/MS)32Chapter 4 Operational Phases and Modes of Operation344.1 Modes of operation344.2 Frame structure344.3 Overview344.3.1 Definitions364.3.2 Additional timing parameters374.3.3 Phase triggers374.4 Clock operation as a function of mode/phase394.5 Power control modes of operation41Chapter 5 Memory Maps445.1 High-level memory map445.2 Alignment issues465.3 Memory-mapped components485.3.1 Interrupt controller485.3.2 Nonvolatile register area485.3.3 RGPIO485.4 Detailed register set495.5 Interrupt vector table565.6 RAM59Chapter 6 Flash Memory Controller606.1 Introduction606.1.1 Overview606.1.2 Features616.2 Theory of operation616.3 Modes of operation626.3.1 Flash IDLE626.3.2 Flash READ626.3.3 Flash PROGRAM626.3.4 Flash ERASE626.4 Flash memory maps636.4.1 Array memory map636.5 Flash registers and control bits646.6 Flash memory map/register definition656.6.1 Flash Options register656.7 Initialization information676.7.1 Factory676.7.2 End user676.8 Programming model676.9 Security68Chapter 7 ROM707.1 Introduction707.2 Boot ROM707.2.1 Boot Step 1: RESET717.2.2 Boot Step 2: Load PC and SSP727.2.3 Boot Step 3: Load configuration parameters727.2.4 Boot steps 4 and 9: For flash boots, jump to flash737.2.5 Boot Step 5: Initialize Command Interpreter747.2.6 Boot Step 6: Launch ROM Command Interpreter757.3 Security and rights management767.3.1 Access and security rules of thumb767.3.2 Security767.4 Rights management777.4.1 Memory-map restrictions777.4.2 Rights-management variables777.5 ROM Command Interpreter797.5.1 Callable utilities797.5.2 Packet transfers and commands overview807.5.3 Common error codes817.5.4 CI_DEV_INFO827.5.5 CI_READ_WRITE847.5.6 CI_ERASE897.5.7 CI_CRC937.5.8 CI_RESET967.5.9 CI_PROTECT and CI_UNPROTECT987.6 User-callable ROM functions997.6.1 RMF_GET_DEVICE_INFO1037.6.2 RMF_FLASH_PROGRAM1047.6.3 RMF_FLASH_ERASE1077.6.4 RMF_FLASH_PROTECT and RMF_FLASH_UNPROTECT1107.6.5 RMF_FLASH_UNSECURE1107.6.6 RMF_CRC111Chapter 8 Slave Port Interface1148.1 Introduction1148.2 I2C features and limitations1168.2.1 I2C features1168.2.2 I2C limitations1178.2.3 SPI features and limitations117Standard SPI pins1188.2.4 SPI features1198.2.5 SPI limitations1208.3 Data coherency issues1208.3.1 Read buffer1218.3.2 Binary semaphore (mutex) operation1228.4 Slave memory map/register definitions1238.4.1 Slave memory map1238.4.2 Slave Port Interface register descriptions1248.4.3 Output interrupt timing1388.5 I2C serial protocol and timing1408.5.1 Baud rates1408.5.2 Serial-addressing1408.5.3 Start, Stop and Repeated Start conditions1408.5.4 Bit transfer1418.5.5 Acknowledge1428.5.6 Slave address1428.5.7 Message format for writing1438.5.8 Message format for reading the platform1458.6 SPI serial protocol and timing1478.6.1 SPI read operation1478.6.2 SPI write operation1498.7 Interrupts1518.7.1 Mailbox interrupt1518.7.2 Semaphore interrupts1518.8 Reset operation151Chapter 9 Inter-Integrated Circuit1529.1 Introduction1529.1.1 Features1529.1.2 Modes of operation1539.1.3 Block diagram1539.2 External signal description1549.2.1 Serial clock line1549.2.2 Serial data line1549.3 Register definitions1559.3.1 I2C memory map1559.3.2 I2C register details1569.4 Functional description1679.4.1 I2C protocol1679.4.2 10-bit address1709.4.3 Address matching1729.5 Resets1729.6 Interrupts1729.6.1 Byte-transfer interrupt1739.6.2 Address-detect interrupt1739.6.3 Exit from Low-Power/Stop modes1739.6.4 Arbitration-lost interrupt1739.6.5 Programmable, input-glitch filter1749.6.6 Address-matching wakeup1749.7 Initialization/application information175Chapter 10 Analog Front End18010.1 Introduction18010.2 Features18010.3 AFE architecture and theory of operation18110.3.1 ADC operation18110.3.2 Accelerometer principle of operation18310.4 Memory map overview186Chapter 11 System Integration Module18811.1 Introduction18811.2 Reset generation19011.2.1 Reset sources19011.2.2 Reset outputs19011.3 Mode control19311.3.1 STOP mode19311.3.2 DEBUG modes19411.4 Oscillator control19511.4.1 General19511.4.2 CPU19511.5 Clock gating19511.6 SIM memory map and registers19611.6.1 SIM memory map19611.6.2 SIM registers descriptions197Chapter 12 On-Chip Oscillator21412.1 Introduction21412.2 High-level overview21412.3 CLKGEN Memory Map/Register Definition21712.3.1 Oscillator Control Register21712.4 Interrupts219Chapter 13 Programmable Delay Block22013.1 Introduction22013.1.1 Features22013.1.2 Modes of operation22013.1.3 Block diagram22113.2 Programmable Delay Block memory map and registers22213.2.1 Programmable Delay Block memory map22213.2.2 Programmable Delay Block registers descriptions22313.2.3 Functional description22713.3 Resets22713.4 Clocks22713.5 Interrupts227Chapter 14 Port Controls22814.1 Port Control customizations22814.1.1 General rules22814.1.2 Exceptions to the general rules22914.1.3 Pins not covered by the port control modules22914.2 Standard pin controls23014.2.1 Pin controls overview23014.3 Port Controls memory map and registers23114.3.1 Port Controls memory map23114.3.2 Port Controls registers232Chapter 15 Rapid GPIO23815.1 Introduction23815.1.1 Overview23815.1.2 Features23915.1.3 Modes of operation24015.2 External signal description24015.2.1 Overview24015.2.2 Detailed Rapid GPIO signal descriptions24015.3 Rapid GPIO memory map/register definitions24115.3.1 Rapid GPIO memory map24115.3.2 Rapid GPIO register descriptions24215.4 Functional description24815.5 Initialization information24815.6 Application information24815.6.1 Application 1: Simple square-wave generation24815.6.2 Application 2: 16-bit message transmission using SPI protocol249Chapter 16 Pin Interrupt Function25216.1 Overview25216.2 Features25216.3 Modes of operation25216.4 Block diagram25316.5 Pin Interrupt signal description25316.6 Pin Interrupt memory map and registers25416.6.1 Pin Interrupt memory map25416.6.2 Register descriptions25416.7 Functional description25616.7.1 External interrupt pin25616.7.2 IRQ edge select25616.7.3 IRQ sensitivity25616.7.4 IRQ interrupts25616.7.5 Clearing an IRQ interrupt request25616.8 Exit from low-power modes25716.8.1 STOP25716.9 Resets25716.10 Interrupts257Chapter 17 16-Bit Modulo Timer25817.1 Introduction25817.2 Features25817.2.1 Block diagram25917.2.2 Modes of operation25917.3 Model-timer memory map/registers26017.3.1 MTIM16 memory map26017.3.2 MTM16 registers26117.4 Functional description26517.4.1 MTIM16 operation example266Chapter 18 Timer/PWM Module26818.1 Introduction26818.1.1 Features26818.1.2 Modes of operation26918.1.3 Block diagram27018.2 Timer/PWM signal description27218.2.1 Timer/PWM detailed signal descriptions27218.3 Timer/PWM memory map/register descriptions27518.3.1 Timer/PWM memory map27518.3.2 Timer/PWM register descriptions27618.4 Functional description28818.4.1 Counter28818.4.2 Channel-mode selection28918.5 Reset overview29318.5.1 General29318.5.2 Description of reset operation29318.6 Interrupts29318.6.1 General29318.6.2 Description of interrupt operation293Chapter 19 Interrupt Controller29619.1 Introduction29619.2 Overview29719.2.1 Features30119.2.2 Modes of operation30219.2.3 Device-specific exception and interrupt vector tables30219.2.4 External signal description30219.3 Interrupt Controller memory map and register definition30219.3.1 Interrupt Controller memory map30319.3.2 Interrupt Controller register descriptions30319.4 Functional description31019.4.1 Handling of non-maskable, level-7 interrupt requests31019.5 Initialization information31019.6 Application information31119.6.1 Emulation of the HCS08’s one-level, IRQ handling31119.6.2 Using INTC_PL6P{7,6} registers31119.6.3 More on software IACKs312Chapter 20 ColdFire Core31420.1 Introduction31420.2 Overview31420.3 Memory map/register description31620.3.1 Data registers31820.3.2 Address Registers31820.3.3 Supervisor/user stack pointers (A7 and OTHER_A7)31920.3.4 Program Counter (PC)32020.3.5 Vector Base Register32120.3.6 CPU Configuration Register32120.3.7 Status Register (SR)32320.4 Functional description32420.4.1 Instruction set architecture32420.4.2 Exception-processing overview32620.4.3 Processor exceptions32920.4.4 Instruction execution timing337Chapter 21 Version 1 ColdFire Debug34621.1 Chip-specific information about CF1_DEBUG34621.2 Introduction34621.2.1 Overview34721.2.2 Features34821.2.3 Modes of operations34821.3 External signal descriptions35121.4 Memory map/register definition35121.4.1 Configuration/Status Register35321.4.2 Extended Configuration/Status Register35621.4.3 Configuration/Status Register 2 (CSR2)36021.4.4 Configuration/Status Register 3 (CSR3)36321.4.5 BDM Address Attribute Register (BAAR)36521.4.6 Address Attribute Trigger Register (AATR)36621.4.7 Trigger Definition Register36721.4.8 Program Counter Breakpoint/Mask Registers37121.4.9 Address Breakpoint Registers37321.4.10 Data Breakpoint and Mask Registers37421.4.11 Resulting set of possible trigger combinations37521.5 Functional description37621.5.1 Background Debug Mode (BDM)37621.5.2 Real-time debug support40821.5.3 Freescale-recommended BDM pinout408Appendix A - Revision History410Size: 1.65 MBPages: 410Language: EnglishOpen manual
