User ManualTable of ContentsCHAPTER 1 OVERVIEW OF FR81 FAMILY CPU151.1 Features of FR81 Family CPU161.2 Changes from the earlier FR Family18CHAPTER 2 MEMORY ARCHITECTURE212.1 Address Space222.1.1 Direct Address Area222.1.2 Vector Table Area232.1.3 20-bit Addressing Area & 32-bit Addressing Area252.2 Data Structure262.2.1 Byte Data262.2.2 Half Word Data262.2.3 Word Data262.2.4 Byte Order272.3 Word Alignment282.3.1 Program Access282.3.2 Data Access28CHAPTER 3 PROGRAMMING MODEL293.1 Register Configuration303.2 General-purpose Registers313.2.1 Configuration of General-purpose Registers313.2.2 Special Usage of General-purpose Registers323.2.3 Relation between Stack Pointer and R15323.3 Dedicated Registers333.3.1 Configuration of Dedicated Registers333.3.2 Program Counter (PC)343.3.3 Program Status (PS)343.3.4 System Status Register (SSR)353.3.5 Interrupt Level Mask Register (ILM)363.3.6 Condition Code Register (CCR)373.3.7 System Condition Code Register (SCR)393.3.8 Return Pointer (RP)403.3.9 System Stack Pointer (SSP)413.3.10 User Stack Pointer (USP)423.3.11 Table Base Register (TBR)433.3.12 Multiplication/Division Register (MDH, MDL)443.3.13 Base Pointer (BP)463.3.14 FPU Control Register (FCR)463.3.15 Exception status register (ESR)513.3.16 Debug Register (DBR)533.4 Floating-point Register54CHAPTER 4 RESET AND "EIT" PROCESSING554.1 Reset564.2 Basic Operations in EIT Processing574.2.1 Types of EIT Processing and Prior Preparation574.2.2 EIT Processing Sequence584.2.3 Recovery from EIT Processing594.3 Processor Operation Status604.4 Exception Processing624.4.1 Invalid Instruction Exception624.4.2 Instruction Access Protection Violation Exception634.4.3 Data Access Protection Violation Exception634.4.4 FPU Exception644.4.5 Instruction Break654.4.6 Guarded Access Break664.5 Interrupts674.5.1 General interrupts674.5.2 Non-maskable Interrupts (NMI)694.5.3 Break Interrupt694.5.4 Data Access Error Interrupt704.6 Traps714.6.1 INT Instructions714.6.2 INTE Instruction714.6.3 Step Trace Traps724.7 Multiple EIT processing and Priority Levels744.7.1 Multiple EIT Processing744.7.2 Priority Levels of EIT Requests754.7.3 EIT Acceptance when Branching Instruction is Executed764.8 Timing When Register Settings Are Reflected774.8.1 Timing when the interrupt enable flag (I) is requested774.8.2 Timing of Reflection of Interrupt Level Mask Register (ILM)784.9 Usage Sequence of General Interrupts794.9.1 Preparation while using general interrupts794.9.2 Processing during an Interrupt Processing Routine804.9.3 Points of Caution while using General Interrupts804.10 Precautions814.10.1 Exceptions in EIT Sequence and RETI Sequence814.10.2 Exceptions in Multiple Load and Multiple Store Instructions814.10.3 Exceptions in Direct Address Transfer Instruction81CHAPTER 5 PIPELINE OPERATION835.1 Instruction execution based on Pipeline845.1.1 Integer Pipeline845.1.2 Floating Point Pipeline865.2 Pipeline Operation and Interrupt Processing875.2.1 Mismatch in Acceptance and Cancellation of Interrupt875.2.2 Method of preventing the mismatched pipeline conditions875.3 Pipeline hazards885.3.1 Occurrence of data hazard885.3.2 Register Bypassing885.3.3 Interlocking895.3.4 Interlocking produced by reference to R15 after Changing the Stack flag (S)895.3.5 Structural Hazard895.3.6 Control Hazard905.4 Non-block loading915.5 Delayed branching processing925.5.1 Example of branching with non-delayed branching instructions925.5.2 Example of processing of delayed branching instruction93CHAPTER 6 INSTRUCTION OVERVIEW956.1 Instruction System966.1.1 Integer Type Instructions966.1.2 Floating Point Type Instructions986.2 Instructions Formats996.2.1 Instructions Notation Formats996.2.2 Addressing Formats1006.2.3 Instruction Formats1016.2.4 Register designated Field1056.3 Data Format1076.3.1 Data Format Used by Integer Type Instructions (Common with All FR Family)1076.3.2 Format Used for Floating Point Type Instructions1086.4 Read-Modify-Write type Instructions1106.5 Branching Instructions and Delay Slot1116.5.1 Delayed Branching Instructions1116.5.2 Specific example of Delayed Branching Instructions1126.5.3 Non-Delayed Branching Instructions1136.6 Step Division Instructions1146.6.1 Signed Division1146.6.2 Unsigned Division115CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS1177.1 ADD (Add 4bit Immediate Data to Destination Register)1197.2 ADD (Add Word Data of Source Register to Destination Register)1217.3 ADD2 (Add 4bit Immediate Data to Destination Register)1237.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register)1257.5 ADDN (Add Immediate Data to Destination Register)1277.6 ADDN (Add Word Data of Source Register to Destination Register)1297.7 ADDN2 (Add Immediate Data to Destination Register)1317.8 ADDSP (Add Stack Pointer and Immediate Data)1337.9 AND (And Word Data of Source Register to Data in Memory)1357.10 AND (And Word Data of Source Register to Destination Register)1377.11 ANDB (And Byte Data of Source Register to Data in Memory)1397.12 ANDCCR (And Condition Code Register and Immediate Data)1417.13 ANDH (And Halfword Data of Source Register to Data in Memory)1437.14 ASR (Arithmetic shift to the Right Direction)1457.15 ASR (Arithmetic shift to the Right Direction)1477.16 ASR2 (Arithmetic shift to the Right Direction)1497.17 BANDH (And 4bit Immediate Data to Higher 4bit of Byte Data in Memory)1517.18 BANDL (And 4bit Immediate Data to Lower 4bit of Byte Data in Memory)1537.19 Bcc (Branch relative if Condition satisfied)1557.20 Bcc:D (Branch relative if Condition satisfied)1577.21 BEORH (Eor 4bit Immediate Data to Higher 4bit of Byte Data in Memory)1597.22 BEORL (Eor 4bit Immediate Data to Lower 4bit of Byte Data in Memory)1617.23 BORH (Or 4bit Immediate Data to Higher 4bit of Byte Data in Memory)1637.24 BORL (Or 4bit Immediate Data to Lower 4bit of Byte Data in Memory)1657.25 BTSTH (Test Higher 4bit of Byte Data in Memory)1677.26 BTSTL (Test Lower 4bit of Byte Data in Memory)1697.27 CALL (Call Subroutine)1717.28 CALL (Call Subroutine)1737.29 CALL:D (Call Subroutine)1757.30 CALL:D (Call Subroutine)1777.31 CMP (Compare Immediate Data and Destination Register)1797.32 CMP (Compare Word Data in Source Register and Destination Register)1817.33 CMP2 (Compare Immediate Data and Destination Register)1837.34 DIV0S (Initial Setting Up for Signed Division)1857.35 DIV0U (Initial Setting Up for Unsigned Division)1877.36 DIV1 (Main Process of Division)1897.37 DIV2 (Correction When Remain is zero)1917.38 DIV3 (Correction When Remain is zero)1937.39 DIV4S (Correction Answer for Signed Division)1957.40 DMOV (Move Word Data from Direct Address to Register)1977.41 DMOV (Move Word Data from Register to Direct Address)1997.42 DMOV (Move Word Data from Direct Address to Post Increment Register Indirect Address)2017.43 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address)2037.44 DMOV (Move Word Data from Direct Address to Pre Decrement Register Indirect Address)2057.45 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address)2077.46 DMOVB (Move Byte Data from Direct Address to Register)2097.47 DMOVB (Move Byte Data from Register to Direct Address)2117.48 DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address)2137.49 DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address)2157.50 DMOVH (Move Halfword Data from Direct Address to Register)2177.51 DMOVH (Move Halfword Data from Register to Direct Address)2197.52 DMOVH (Move Halfword Data from Direct Address to Post Increment Register Indirect Address)2217.53 DMOVH (Move Halfword Data from Post Increment Register Indirect Address to Direct Address)2237.54 ENTER (Enter Function)2257.55 EOR (Exclusive Or Word Data of Source Register to Data in Memory)2277.56 EOR (Exclusive Or Word Data of Source Register to Destination Register)2297.57 EORB (Exclusive Or Byte Data of Source Register to Data in Memory)2317.58 EORH (Exclusive Or Halfword Data of Source Register to Data in Memory)2337.59 EXTSB (Sign Extend from Byte Data to Word Data)2357.60 EXTSH (Sign Extend from Byte Data to Word Data)2377.61 EXTUB (Unsign Extend from Byte Data to Word Data)2397.62 EXTUH (Unsign Extend from Byte Data to Word Data)2417.63 FABSs (Single Precision Floating Point Absolute Value)2437.64 FADDs (Single Precision Floating Point Add)2447.65 FBcc (Floating Point Conditional Branch)2467.66 FBcc:D (Floating Point Conditional Branch with Delay Slot)2487.67 FCMPs (Single Precision Floating Point Compare)2507.68 FDIVs (Single Precision Floating Point Division)2527.69 FiTOs (Convert from Integer to Single Precision Floating Point)2547.70 FLD (Single Precision Floating Point Data Load)2567.71 FLD (Single Precision Floating Point Data Load)2577.72 FLD (Single Precision Floating Point Data Load)2587.73 FLD (Single Precision Floating Point Data Load)2597.74 FLD (Single Precision Floating Point Data Load)2607.75 FLD (Load Word Data in Memory to Floating Register)2617.76 FLDM (Single Precision Floating Point Data Load to Multiple Register)2627.77 FMADDs (Single Precision Floating Point Multiply and Add)2647.78 FMOVs (Single Precision Floating Point Move)2667.79 FMSUBs (Single Precision Floating Point Multiply and Subtract)2677.80 FMULs (Single Precision Floating Point Multiply)2697.81 FNEGs (Single Precision Floating Point sign reverse)2717.82 FSQRTs (Single Precision Floating Point Square Root)2727.83 FST (Single Precision Floating Point Data Store)2737.84 FST (Single Precision Floating Point Data Store)2747.85 FST (Single Precision Floating Point Data Store)2757.86 FST (Single Precision Floating Point Data Store)2767.87 FST (Single Precision Floating Point Data Store)2777.88 FST (Store Word Data in Floating Point Register to Memory)2787.89 FSTM (Single Precision Floating Point Data Store from Multiple Register)2797.90 FsTOi (Convert from Single Precision Floating Point to Integer)2817.91 FSUBs (Single Precision Floating Point Subtract)2837.92 INT (Software Interrupt)2857.93 INTE (Software Interrupt for Emulator)2877.94 JMP (Jump)2897.95 JMP:D (Jump)2917.96 LCALL (Long Call Subroutine)2937.97 LCALL:D (Long Call Subroutine)2947.98 LD (Load Word Data in Memory to Register)2957.99 LD (Load Word Data in Memory to Register)2977.100 LD (Load Word Data in Memory to Register)2997.101 LD (Load Word Data in Memory to Register)3017.102 LD (Load Word Data in Memory to Register)3037.103 LD (Load Word Data in Memory to Register)3057.104 LD (Load Word Data in Memory to Register)3067.105 LD (Load Word Data in Memory to Program Status Register)3087.106 LDI:20 (Load Immediate 20bit Data to Destination Register)3107.107 LDI:32 (Load Immediate 32 bit Data to Destination Register)3127.108 LDI:8 (Load Immediate 8bit Data to Destination Register)3147.109 LDM0 (Load Multiple Registers)3167.110 LDM1 (Load Multiple Registers)3187.111 LDUB (Load Byte Data in Memory to Register)3207.112 LDUB (Load Byte Data in Memory to Register)3227.113 LDUB (Load Byte Data in Memory to Register)3247.114 LDUB (Load Byte Data in Memory to Register)3267.115 LDUH (Load Halfword Data in Memory to Register)3277.116 LDUH (Load Halfword Data in Memory to Register)3297.117 LDUH (Load Halfword Data in Memory to Register)3317.118 LDUH (Load Halfword Data in Memory to Register)3337.119 LEAVE (Leave Function)3347.120 LSL (Logical Shift to the Left Direction)3367.121 LSL (Logical Shift to the Left Direction)3387.122 LSL2 (Logical Shift to the Left Direction)3407.123 LSR (Logical Shift to the Right Direction)3427.124 LSR (Logical Shift to the Right Direction)3447.125 LSR2 (Logical Shift to the Right Direction)3467.126 MOV (Move Word Data in Source Register to Destination Register)3487.127 MOV (Move Word Data in Source Register to Destination Register)3507.128 MOV (Move Word Data in Program Status Register to Destination Register)3527.129 MOV (Move Word Data in Source Register to Destination Register)3547.130 MOV (Move Word Data in Source Register to Program Status Register)3567.131 MOV (Move Word Data in General Purpose Register to Floating Point Register)3587.132 MOV (Move Word Data in Floating Point Register to General Purpose Register)3597.133 MUL (Multiply Word Data)3607.134 MULH (Multiply Halfword Data)3627.135 MULU (Multiply Unsigned Word Data)3647.136 MULUH (Multiply Unsigned Halfword Data)3667.137 NOP (No Operation)3687.138 OR (Or Word Data of Source Register to Data in Memory)3707.139 OR (Or Word Data of Source Register to Destination Register)3727.140 ORB (Or Byte Data of Source Register to Data in Memory)3747.141 ORCCR (Or Condition Code Register and Immediate Data)3767.142 ORH (Or Halfword Data of Source Register to Data in Memory)3787.143 RET (Return from Subroutine)3807.144 RET:D (Return from Subroutine)3827.145 RETI (Return from Interrupt)3847.146 SRCH0 (Search First Zero bit position distance From MSB)3877.147 SRCH1 (Search First One bit position distance From MSB)3897.148 SRCHC (Search First bit value change position distance From MSB)3917.149 ST (Store Word Data in Register to Memory)3937.150 ST (Store Word Data in Register to Memory)3957.151 ST (Store Word Data in Register to Memory)3977.152 ST (Store Word Data in Register to Memory)3997.153 ST (Store Word Data in Register to Memory)4017.154 ST (Store Word Data in Register to Memory)4037.155 ST (Store Word Data in Register to Memory)4047.156 ST (Store Word Data in Program Status Register to Memory)4067.157 STB (Store Byte Data in Register to Memory)4087.158 STB (Store Byte Data in Register to Memory)4107.159 STB (Store Byte Data in Register to Memory)4127.160 STB (Store Byte Data in Register to Memory)4147.161 STH (Store Halfword Data in Register to Memory)4157.162 STH (Store Halfword Data in Register to Memory)4177.163 STH (Store Halfword Data in Register to Memory)4197.164 STH (Store Halfword Data in Register to Memory)4217.165 STILM (Set Immediate Data to Interrupt Level Mask Register)4227.166 STM0 (Store Multiple Registers)4247.167 STM1 (Store Multiple Registers)4267.168 SUB (Subtract Word Data in Source Register from Destination Register)4287.169 SUBC (Subtract Word Data in Source Register and Carry bit from Destination Register)4307.170 SUBN (Subtract Word Data in Source Register from Destination Register)4327.171 XCHB (Exchange Byte Data)434APPENDIX437APPENDIX A Instruction Lists438A.1 Meaning of Symbols439A.1.1 Mnemonic and Operation Columns439A.1.2 Operation Column444A.1.3 Format Column445A.1.4 OP Column445A.1.5 CYC Column446A.1.6 FLAG Column447A.1.7 RMW Column447A.1.8 Reference Column447A.2 Instruction Lists448A.3 List of Instructions that can be positioned in the Delay Slot462APPENDIX B Instruction Maps464B.1 Instruction Maps465B.2 Extension Instruction Maps466APPENDIX C Supplemental Explanation about FPU Exception Processing469C.1 Conformity with IEEE754-1985 Standard469C.2 FPU Exceptions470C.3 Round Processing472Size: 3.42 MBPages: 490Language: EnglishOpen manual