User ManualTable of Contents1. Introduction111.1 Chapter Outline111.2 Server Board Use Disclaimer112. Server Board Overview132.1 Server Board Feature Set132.2 Server Board Layout162.2.1 Server Board Connector and Component Layout172.2.2 Server Board Mechanical Drawings192.2.3 Server Board ATX I/O Layout253. Functional Architecture263.1 Intel® 5000P / 5000X Memory Controller Hub (MCH)283.1.1 System Bus Interface283.1.2 Processor Support283.1.2.1 Processor Population Rules293.1.2.2 Common Enabling Kit (CEK) Design Support293.1.3 Memory Sub-system313.1.3.1 Memory RASUM Features323.1.3.2 Supported Memory333.1.3.3 DIMM Population Rules and Supported DIMM Configurations333.1.3.3.1 Minimum Non-Mirrored Mode Configuration363.1.3.4 Non-mirrored Mode Memory Upgrades373.1.3.4.1 Mirrored Mode Memory Configuration383.1.3.4.2 Sparing Mode Memory Configuration383.1.3.4.2.1 Single Branch Mode Sparing393.1.3.4.2.2 Dual Branch Mode Sparing403.1.4 Snoop Filter (5000X MCH only)403.2 Enterprise South Bridge (ESB2-E)403.2.1 PCI Sub-system413.2.1.1 PCI32: 32-bit, 33-MHz PCI Sub-system423.2.1.2 PXA: 64-bit, 133-MHz PCI Sub-system423.2.1.3 PE0: One x4 PCI Express* Bus Segment423.2.1.4 PE1: One x4 PCI Express* Bus Segment423.2.1.5 PE2: One x4 PCI Express* Bus Segment423.2.1.6 PE4, PE5: Two x4 PCI Express* Bus Segments423.2.1.7 PE6, PE7: Two x4 PCI Express* Bus Segments423.2.1.8 PCI Express* Riser Slot423.2.2 Serial ATA Support433.2.2.1 Intel® Embedded Server RAID Technology II Support433.2.2.2 Intel® Embedded Server RAID Technology Option ROM443.2.3 Parallel ATA (PATA) Support443.2.4 USB 2.0 Support443.3 Video Support443.3.1 Video Modes463.3.2 Video Memory Interface463.3.3 Dual Video463.4 SAS Controller473.4.1 SAS RAID Support473.4.2 SAS / SATA Connector Sharing473.5 Network Interface Controller (NIC)473.5.1 Intel® I/O Acceleration Technolgy483.5.2 MAC Address Definition483.6 Super I/O483.6.1 Serial Ports493.6.2 Floppy Disk Controller493.6.3 Keyboard and Mouse Support493.6.4 Wake-up Control493.6.5 System Health Support494. Platform Management505. Connector / Header Locations and Pin-outs525.1 Board Connector Information525.2 Power Connectors535.3 System Management Headers555.3.1 Intel® Remote Management Module (Intel® RMM) Connector555.3.2 LCP / AUX IPMB Header565.3.3 IPMB Header575.3.4 HSBP Header575.3.5 SGPIO Header575.3.6 SES I2C575.3.7 HDD Activity LED Header585.4 Front Panel Connector585.5 I/O Connectors585.5.1 VGA Connector585.5.2 NIC Connectors595.5.3 IDE Connector595.5.4 Intel® Remote Management Module NIC Connector605.5.5 SATA / SAS Connectors625.5.6 Serial Port Connectors625.5.7 Keyboard and Mouse Connector635.5.8 USB Connector645.6 Fan Headers656. Jumper Blocks676.1 CMOS Clear and Password Reset Usage Procedure686.2 BMC Force Update Procedure686.3 BIOS Select Jumper697. Intel® Light Guided Diagnostics707.1 5 Volt Standby LED707.2 Fan Fault LEDs717.3 System ID LED and System Status LED727.3.1 System Status LED – BMC Initialization737.4 DIMM Fault LEDs757.5 Processor Fault LEDs767.6 Post Code Diagnostic LEDs778. Design and Environmental Specifications788.1 Server Boards S5000PSL and S5000XSL Design Specifications788.2 Server Board Power Requirements798.2.1 Processor Power Support808.3.1 Grounding818.3.2 Standby Outputs818.3.3 Remote Sense818.3.4 Voltage Regulation828.3.5 Dynamic Loading828.3.6 Capacitive Loading838.3.7 Ripple / Noise838.3.8 Timing Requirements838.3.9 Residual Voltage Immunity in Standby Mode869. Regulatory and Certification Information879.1.1 Product Safety Compliance879.1.2 Product EMC Compliance – Class A Compliance879.1.3 Certifications / Registrations / Declarations889.3.1 FCC Verification Statement (USA)899.3.2 ICES-003 (Canada)899.3.3 Europe (CE Declaration of Conformity)909.3.4 VCCI (Japan)909.3.5 BSMI (Taiwan)909.3.6 RRL (Korea)909.3.7 CNCA (CCC-China)91Size: 3.01 MBPages: 120Language: EnglishOpen manual