Microchip Technology MCP6241-E/SN Linear IC SOIC-8 User Manuals

Table of Contents

• 1.0 Electrical Characteristics

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  • 1.1 Test Circuits

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    • FIGURE 1-1: AC and DC Test Circuit for Most Non-Inverting Gain Conditions.

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    • FIGURE 1-2: AC and DC Test Circuit for Most Inverting Gain Conditions.

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• 2.0 Typical Performance Curves

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  • FIGURE 2-1: Input Offset Voltage.

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  • FIGURE 2-2: PSRR, CMRR vs. Frequency.

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  • FIGURE 2-3: Input Bias Current at +85C.

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  • FIGURE 2-4: CMRR, PSRR vs. Ambient Temperature.

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  • FIGURE 2-5: Open-Loop Gain, Phase vs. Frequency.

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  • FIGURE 2-6: Input Bias Current at +125C.

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  • FIGURE 2-7: Input Noise Voltage Density vs. Frequency.

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  • FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V.

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  • FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V.

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  • FIGURE 2-10: Input Offset Voltage Drift.

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  • FIGURE 2-11: Input Offset Voltage vs. Output Voltage.

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  • FIGURE 2-12: Output Short-Circuit Current vs. Ambient Temperature.

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  • FIGURE 2-13: Slew Rate vs. Ambient Temperature.

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  • FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude.

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  • FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency.

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  • FIGURE 2-16: Small-Signal, Non-Inverting Pulse Response.

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  • FIGURE 2-17: Large-Signal, Non-Inverting Pulse Response.

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  • FIGURE 2-18: Quiescent Current vs. Power Supply Voltage.

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  • FIGURE 2-19: Measured Input Current vs. Input Voltage (below VSS).

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• 3.0 Pin Descriptions

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  • TABLE 3-1: Pin Function Table for Single Op Amps

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  • TABLE 3-2: Pin Function Table for Dual and Quad Op Amps

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  • 3.1 Analog Outputs

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  • 3.2 Analog Inputs

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  • 3.3 Power Supply (VSS and VDD)

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  • 3.4 Exposed Thermal Pad (EP)

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• 4.0 Application infoRmation

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  • 4.1 Rail-to-Rail Inputs

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    • FIGURE 4-1: The MCP6241/1R/1U/2/4 Show No Phase Reversal.

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    • FIGURE 4-2: Simplified Analog Input ESD Structures.

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    • FIGURE 4-3: Protecting the Analog Inputs.

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  • 4.2 Rail-to-Rail Output

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  • 4.3 Capacitive Loads

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    • FIGURE 4-4: Output Resistor, RISO stabilizes large capacitive loads.

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    • FIGURE 4-5: Recommended RISO Values for Capacitive Loads.

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  • 4.4 Supply Bypass

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  • 4.5 Unused Op Amps

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    • FIGURE 4-6: Unused Op Amps.

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  • 4.6 PCB Surface Leakage

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    • FIGURE 4-7: Example Guard Ring Layout for Inverting Gain.

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  • 4.7 Application Circuits

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    • FIGURE 4-8: Summing Amplifier Circuit.

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    • FIGURE 4-9: Effect of Parasitic Capacitance at the Input.

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• 5.0 Design AIDS

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  • 5.1 SPICE Macro Model

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  • 5.2 Mindi™ Circuit Designer & Simulator

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  • 5.3 Microchip Advanced Part Selector (MAPS)

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  • 5.4 Analog Demonstration and Evaluation Boards

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  • 5.5 Application Notes

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• 6.0 Packaging Information

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  • 6.1 Package Marking Information

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