Manuels d'utilisation pour Microchip Technology MCP6241-E/SN Linear IC SOIC-8

Table des matières

• 1.0 Electrical Characteristics

  3
  • 1.1 Test Circuits

    4
    • FIGURE 1-1: AC and DC Test Circuit for Most Non-Inverting Gain Conditions.

      4
    • FIGURE 1-2: AC and DC Test Circuit for Most Inverting Gain Conditions.

      4
• 2.0 Typical Performance Curves

  5
  • FIGURE 2-1: Input Offset Voltage.

    5
  • FIGURE 2-2: PSRR, CMRR vs. Frequency.

    5
  • FIGURE 2-3: Input Bias Current at +85C.

    5
  • FIGURE 2-4: CMRR, PSRR vs. Ambient Temperature.

    5
  • FIGURE 2-5: Open-Loop Gain, Phase vs. Frequency.

    5
  • FIGURE 2-6: Input Bias Current at +125C.

    5
  • FIGURE 2-7: Input Noise Voltage Density vs. Frequency.

    6
  • FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V.

    6
  • FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V.

    6
  • FIGURE 2-10: Input Offset Voltage Drift.

    6
  • FIGURE 2-11: Input Offset Voltage vs. Output Voltage.

    6
  • FIGURE 2-12: Output Short-Circuit Current vs. Ambient Temperature.

    6
  • FIGURE 2-13: Slew Rate vs. Ambient Temperature.

    7
  • FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude.

    7
  • FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency.

    7
  • FIGURE 2-16: Small-Signal, Non-Inverting Pulse Response.

    7
  • FIGURE 2-17: Large-Signal, Non-Inverting Pulse Response.

    7
  • FIGURE 2-18: Quiescent Current vs. Power Supply Voltage.

    7
  • FIGURE 2-19: Measured Input Current vs. Input Voltage (below VSS).

    8
• 3.0 Pin Descriptions

  9
  • TABLE 3-1: Pin Function Table for Single Op Amps

    9
  • TABLE 3-2: Pin Function Table for Dual and Quad Op Amps

    9
  • 3.1 Analog Outputs

    9
  • 3.2 Analog Inputs

    9
  • 3.3 Power Supply (VSS and VDD)

    9
  • 3.4 Exposed Thermal Pad (EP)

    9
• 4.0 Application infoRmation

  11
  • 4.1 Rail-to-Rail Inputs

    11
    • FIGURE 4-1: The MCP6241/1R/1U/2/4 Show No Phase Reversal.

      11
    • FIGURE 4-2: Simplified Analog Input ESD Structures.

      11
    • FIGURE 4-3: Protecting the Analog Inputs.

      11
  • 4.2 Rail-to-Rail Output

    12
  • 4.3 Capacitive Loads

    12
    • FIGURE 4-4: Output Resistor, RISO stabilizes large capacitive loads.

      12
    • FIGURE 4-5: Recommended RISO Values for Capacitive Loads.

      12
  • 4.4 Supply Bypass

    12
  • 4.5 Unused Op Amps

    12
    • FIGURE 4-6: Unused Op Amps.

      12
  • 4.6 PCB Surface Leakage

    13
    • FIGURE 4-7: Example Guard Ring Layout for Inverting Gain.

      13
  • 4.7 Application Circuits

    13
    • FIGURE 4-8: Summing Amplifier Circuit.

      13
    • FIGURE 4-9: Effect of Parasitic Capacitance at the Input.

      14
• 5.0 Design AIDS

  15
  • 5.1 SPICE Macro Model

    15
  • 5.2 Mindi™ Circuit Designer & Simulator

    15
  • 5.3 Microchip Advanced Part Selector (MAPS)

    15
  • 5.4 Analog Demonstration and Evaluation Boards

    15
  • 5.5 Application Notes

    15
• 6.0 Packaging Information

  17
  • 6.1 Package Marking Information

    17