Microchip Technology MCU PIC10F322T-I/OT SOT-23-6 MCP User Manuals

Table of Contents

• High-Performance RISC CPU:

  3
• Special Microcontroller Features:

  3
• Low-Power Features (PIC10LF320/322):

  3
• Peripheral Features:

  3
• TABLE 1: PIC10(L)F320/322 Feature Summary

  4
• TABLE 2: 6 and 8-Pin Allocation Table (PIC10(L)F320/322)

  4
• Table of Contents

  5
• Most Current Data Sheet

  6
• Errata

  6
• Customer Notification System

  6
• 1.0 Device Overview

  7
  • TABLE 1-1: Device Peripheral Summary

    7
  • FIGURE 1-1: PIC10(L)F320/322 Block Diagram

    8
  • TABLE 1-2: PIC10(L)F320/322 Pinout Description

    9
• 2.0 Memory Organization

  11
  • 2.1 Program Memory Organization

    11
    • TABLE 2-1: Device Sizes and Addresses

      11
    • FIGURE 2-1: Program Memory Map And Stack For PIC10(L)F320

      12
    • FIGURE 2-2: Program Memory Map And Stack For PIC10(L)F322

      12
  • 2.2 Data Memory Organization

    13
    • 2.2.1 General Purpose Register File

      13
    • 2.2.2 Special Function Registers

      13
      • Register 2-1: STATUS: STATUS Register

        15
    • 2.2.3 Device Memory Maps

      16
      • TABLE 2-2: PIC10(L)F320/322 Memory Map (Bank 0)

        16
      • TABLE 2-3: Special Function Register Summary (Bank 0)

        17
  • 2.3 PCL and PCLATH

    19
    • FIGURE 2-3: Loading of PC in Different Situations

      19
    • 2.3.1 Modifying PCL

      19
    • 2.3.2 Stack

      19
  • 2.4 Indirect Addressing, INDF and FSR Registers

    19
    • EXAMPLE 2-1: Indirect Addressing

      19
    • FIGURE 2-4: Direct/Indirect Addressing PIC10(L)F320/322

      20
• 3.0 Device Configuration

  21
  • 3.1 Configuration Word

    21
    • Register 3-1: CONFIG: Configuration Word

      22
  • 3.2 Code Protection

    24
    • 3.2.1 Program Memory Protection

      24
  • 3.3 Write Protection

    24
  • 3.4 User ID

    24
  • 3.5 Device ID and Revision ID

    25
    • Register 3-2: DEVICEID: Device ID Register(1)

      25
• 4.0 Oscillator Module

  27
  • 4.1 Overview

    27
    • FIGURE 4-1: PIC10(L)F320/322 Clock Source Block Diagram

      27
  • 4.2 Clock Source Modes

    28
  • 4.3 Internal Clock Modes

    28
    • 4.3.1 INTOSC Mode

      28
    • 4.3.2 Frequency Select Bits (IRCF)

      28
    • 4.3.3 Reference Clock Output Control

      29
      • Register 4-1: CLKRCON – Reference Clock Control Register

        29
  • 4.4 Oscillator Control Registers

    30
    • 4.4.1 Oscillator Control

      30
      • Register 4-2: OSCCON: Oscillator Control Register

        30
  • 4.5 External Clock Mode

    31
    • 4.5.1 EC Mode

      31
      • TABLE 4-1: Summary of Registers Associated with Clock Sources

        31
      • TABLE 4-2: Summary of cONFIGURATION wORD with Clock Sources

        31
• 5.0 Resets

  33
  • FIGURE 5-1: Simplified Block Diagram Of On-Chip Reset Circuit

    33
  • 5.1 Power-on Reset (POR)

    34
    • 5.1.1 Power-up Timer (PWRT)

      34
  • 5.2 Brown-Out Reset (BOR)

    34
    • TABLE 5-1: BOR Operating Modes

      34
    • 5.2.1 BOR is Always On

      34
    • 5.2.2 BOR is Off in Sleep

      34
    • 5.2.3 BOR Controlled by Software

      34
      • FIGURE 5-2: Brown-Out Situations

        35
      • Register 5-1: BORCON: Brown-out Reset Control Register

        35
  • 5.3 Low-Power Brown-out Reset (LPBOR)

    36
    • 5.3.1 Enabling LPBOR

      36
  • 5.4 MCLR

    36
    • TABLE 5-2: MCLR Configuration

      36
    • 5.4.1 MCLR Enabled

      36
    • 5.4.2 MCLR Disabled

      36
  • 5.5 Watchdog Timer (WDT) Reset

    36
  • 5.6 Programming Mode ICSP Exit

    36
  • 5.7 Power-Up Timer

    36
  • 5.8 Start-up Sequence

    36
    • FIGURE 5-3: Reset Start-Up Sequence

      37
  • 5.9 Determining the Cause of a Reset

    38
    • TABLE 5-3: Reset Status Bits and Their Significance

      38
    • TABLE 5-4: Reset Condition for Special Registers

      38
  • 5.10 Power Control (PCON) Register

    39
    • Register 5-2: PCON: Power Control Register

      39
    • TABLE 5-5: Summary Of Registers Associated With Resets

      39
    • TABLE 5-6: Summary of cONFIGURATION wORD with Resets

      39
• 6.0 Interrupts

  41
  • FIGURE 6-1: Interrupt Logic

    41
  • 6.1 Operation

    42
  • 6.2 Interrupt Latency

    42
    • FIGURE 6-2: Interrupt Latency

      43
    • FIGURE 6-3: INT Pin Interrupt Timing

      44
  • 6.3 Interrupts During Sleep

    45
  • 6.4 INT Pin

    45
  • 6.5 Context Saving During Interrupts

    45
    • EXAMPLE 6-1: Saving Status and W Registers in RAM

      45
  • 6.6 Interrupt Control Registers

    46
    • 6.6.1 INTCON Register

      46
      • Register 6-1: INTCON: Interrupt Control Register

        46
    • 6.6.2 PIE1 Register

      47
      • Register 6-2: PIE1: Peripheral Interrupt Enable Register 1

        47
    • 6.6.3 PIR1 Register

      48
      • Register 6-3: PIR1: Peripheral Interrupt Request Register 1

        48
      • TABLE 6-1: Summary of Registers Associated with Interrupts

        49
• 7.0 Power-Down Mode (Sleep)

  51
  • 7.1 Wake-up from Sleep

    51
    • 7.1.1 Wake-up Using Interrupts

      52
      • FIGURE 7-1: Wake-Up From Sleep Through Interrupt

        52
      • TABLE 7-1: Summary of Registers Associated with pOWER-dOWN mODE

        52
• 8.0 Watchdog Timer

  53
  • FIGURE 8-1: Watchdog Timer Block Diagram

    53
  • 8.1 Independent Clock Source

    54
  • 8.2 WDT Operating Modes

    54
    • 8.2.1 WDT Is Always On

      54
    • 8.2.2 WDT Is Off In Sleep

      54
    • 8.2.3 WDT Controlled By Software

      54
      • TABLE 8-1: WDT Operating Modes

        54
  • 8.3 Time-Out Period

    54
  • 8.4 Clearing the WDT

    54
  • 8.5 Operation During Sleep

    54
    • TABLE 8-2: WDT Clearing Conditions

      54
  • 8.6 Watchdog Control Register

    55
    • Register 8-1: WDTCON: Watchdog Timer Control Register

      55
    • TABLE 8-3: Summary of Registers Associated with Watchdog Timer

      56
    • TABLE 8-4: Summary of cONFIGURATION wORD with Watchdog Timer

      56
• 9.0 Flash Program Memory Control

  57
  • 9.1 PMADRL and PMADRH Registers

    57
    • 9.1.1 PMCON1 and PMCON2 Registers

      57
  • 9.2 Flash Program Memory Overview

    57
    • TABLE 9-1: Flash Memory Organization By Device

      58
    • 9.2.1 Reading the Flash Program Memory

      58
      • FIGURE 9-1: Flash Program Memory Read Flowchart

        58
      • FIGURE 9-2: Flash Program Memory Read Cycle Execution

        59
      • EXAMPLE 9-1: Flash PROGRAM MEMORY Read

        59
    • 9.2.2 Flash Memory Unlock Sequence

      60
      • FIGURE 9-3: Flash Program Memory Unlock Sequence Flowchart

        60
    • 9.2.3 Erasing Flash Program Memory

      61
      • FIGURE 9-4: Flash Program Memory Erase Flowchart

        61
      • EXAMPLE 9-2: Erasing One Row of Program Memory

        62
    • 9.2.4 Writing to Flash Program Memory

      63
      • FIGURE 9-5: Block WRITES to Flash Program Memory With 16 write latches

        64
      • FIGURE 9-6: Flash Program Memory Write Flowchart

        65
      • EXAMPLE 9-3: Writing to Flash Program Memory

        66
  • 9.3 Modifying Flash Program Memory

    67
    • FIGURE 9-7: Flash Program Memory Modify Flowchart

      67
  • 9.4 User ID, Device ID and Configuration Word Access

    68
    • TABLE 9-2: User ID, Device ID and Configuration Word Access (cfgs = 1)

      68
    • EXAMPLE 9-4: Configuration Word and Device ID Access

      68
  • 9.5 Write Verify

    69
    • FIGURE 9-8: Flash Program Memory Verify Flowchart

      69
  • 9.6 Flash Program Memory Control Registers

    70
    • Register 9-1: PMDATL: Program Memory Data Low

      70
    • Register 9-2: PMDATH: Program Memory Data hIGH

      70
    • Register 9-3: PMADRL: Program Memory Address Low

      71
    • Register 9-4: PMADRH: Program Memory Address hIGH

      71
    • Register 9-5: PMCON1: Program Memory Control 1 Register

      72
    • Register 9-6: PMCON2: Program Memory Control 2 Register

      73
    • TABLE 9-3: Summary of Registers Associated with Flash Program Memory

      73
    • TABLE 9-4: Summary of cONFIGURATION wORD with Flash Program Memory

      73
• 10.0 I/O Port

  75
  • FIGURE 10-1: I/O Port Operation

    75
  • EXAMPLE 10-1: Initializing PORTA

    75
  • 10.1 PORTA Registers

    76
    • 10.1.1 Weak Pull-ups

      76
    • 10.1.2 ANSELA Register

      76
    • 10.1.3 PORTA Functions and Output Priorities

      76
      • TABLE 10-1: PORTA Output Priority

        76
      • Register 10-1: PORTA: PORTA Register

        77
      • Register 10-2: TRISA: PORTA Tri-State Register

        77
      • Register 10-3: LATA: PORTA Data Latch Register

        78
      • Register 10-4: ANSELA: PORTA Analog Select Register

        78
      • Register 10-5: WPUA: Weak Pull-UP PORTA Register

        79
      • TABLE 10-2: Summary of Registers Associated with PORTA

        80
• 11.0 Interrupt-On-Change

  81
  • 11.1 Enabling the Module

    81
  • 11.2 Individual Pin Configuration

    81
  • 11.3 Interrupt Flags

    81
  • 11.4 Clearing Interrupt Flags

    81
    • EXAMPLE 11-1:

      81
  • 11.5 Operation in Sleep

    81
    • FIGURE 11-1: Interrupt-On-Change Block Diagram

      82
  • 11.6 Interrupt-On-Change Registers

    83
    • Register 11-1: IOCAP: Interrupt-on-Change PORTA Positive Edge Register

      83
    • Register 11-2: IOCAN: Interrupt-on-Change PORTA Negative Edge Register

      83
    • Register 11-3: IOCAF: Interrupt-on-Change PORTA Flag Register

      84
    • TABLE 11-1: Summary of Registers Associated with Interrupt-on-Change

      84
• 12.0 Fixed Voltage Reference (FVR)

  85
  • 12.1 Independent Gain Amplifiers

    85
  • 12.2 FVR Stabilization Period

    85
    • FIGURE 12-1: Voltage Reference Block Diagram

      85
    • TABLE 12-1: Peripherals Requiring the Fixed Voltage Reference (FVR)

      85
  • 12.3 FVR Control Registers

    86
    • Register 12-1: FVRCON: Fixed Voltage Reference Control Register

      86
    • TABLE 12-2: Summary of Registers Associated with Fixed Voltage Reference

      86
• 13.0 Internal Voltage Regulator (IVR)

  87
  • TABLE 13-1: IVR Power modes - REGULATED

    87
  • Register 13-1: VREGCON: Voltage Regulator Control Register

    88
• 14.0 Temperature Indicator Module

  89
  • 14.1 Circuit Operation

    89
    • EQUATION 14-1: Vout Ranges

      89
    • FIGURE 14-1: Temperature Circuit Diagram

      89
  • 14.2 Minimum Operating Vdd vs. Minimum Sensing Temperature

    89
    • TABLE 14-1: Recommended Vdd vs. Range

      89
  • 14.3 Temperature Output

    89
  • 14.4 ADC Acquisition Time

    89
    • TABLE 14-2: Summary of Registers

      90
• 15.0 Analog-to-Digital Converter (ADC) Module

  91
  • FIGURE 15-1: ADC Simplified Block Diagram

    91
  • 15.1 ADC Configuration

    92
    • 15.1.1 Port Configuration

      92
    • 15.1.2 Channel Selection

      92
    • 15.1.3 ADC Voltage Reference

      92
    • 15.1.4 Conversion Clock

      92
      • TABLE 15-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies

        93
      • FIGURE 15-2: Analog-to-Digital Conversion Tad Cycles

        93
    • 15.1.5 Interrupts

      94
  • 15.2 ADC Operation

    94
    • 15.2.1 Starting a Conversion

      94
    • 15.2.2 Completion of a Conversion

      94
    • 15.2.3 Terminating a conversion

      94
    • 15.2.4 ADC Operation During Sleep

      94
    • 15.2.5 A/D Conversion Procedure

      95
  • 15.3 ADC Register Definitions

    96
    • Register 15-1: ADCON: A/D Control Register 0

      96
    • Register 15-2: ADRES: ADC Result Register

      97
  • 15.4 A/D Acquisition Requirements

    98
    • EQUATION 15-1: Acquisition Time Example

      98
    • FIGURE 15-3: Analog Input Model

      99
    • FIGURE 15-4: ADC Transfer Function

      99
    • TABLE 15-2: Summary of Registers Associated with ADC

      100
• 16.0 Timer0 Module

  101
  • 16.1 Timer0 Operation

    101
    • 16.1.1 8-bit Timer Mode

      101
    • 16.1.2 8-Bit Counter Mode

      101
      • FIGURE 16-1: Block Diagram of the Timer0 Prescaler

        101
    • 16.1.3 Software Programmable Prescaler

      102
    • 16.1.4 Timer0 Interrupt

      102
    • 16.1.5 8-BIT Counter Mode Synchronization

      102
      • Register 16-1: OPTION_REG: OPTION Register

        103
      • TABLE 16-1: Summary of Registers Associated with Timer0

        103
• 17.0 Timer2 Module

  105
  • 17.1 Timer2 Operation

    105
    • FIGURE 17-1: Timer2 Block Diagram

      105
    • Register 17-1: T2CON: Timer2 Control Register

      106
    • TABLE 17-1: Summary of Registers Associated With Timer2

      106
• 18.0 Pulse-Width Modulation (PWM) Module

  107
  • FIGURE 18-1: Simplified PWM Block Diagram

    107
  • FIGURE 18-2: PWM Output

    107
  • 18.1 PWMx Pin Configuration

    108
    • 18.1.1 Fundamental Operation

      108
    • 18.1.2 PWM OUTPUT Polarity

      108
    • 18.1.3 PWM period

      108
      • EQUATION 18-1: PWM Period

        108
    • 18.1.4 PWM Duty Cycle

      108
      • EQUATION 18-2: Pulse Width

        108
      • EQUATION 18-3: Duty Cycle Ratio

        108
    • 18.1.5 PWM Resolution

      109
      • EQUATION 18-4: PWM Resolution

        109
      • TABLE 18-1: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)

        109
      • TABLE 18-2: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)

        109
    • 18.1.6 Operation in Sleep Mode

      109
    • 18.1.7 Changes in System Clock Frequency

      109
    • 18.1.8 Effects of Reset

      109
    • 18.1.9 Setup for PWM Operation using PWMx Pins

      110
  • 18.2 PWM Register Definitions

    111
    • Register 18-1: PWMxCON: PWM Control Register

      111
    • Register 18-2: PWMXDCH: PWM Duty Cycle High Bits

      112
    • Register 18-3: PWMxDCL: PWM Duty Cycle LOW Bits

      112
    • TABLE 18-3: Summary of Registers Associated with PWM

      112
• 19.0 Configurable Logic Cell (CLC)

  113
  • FIGURE 19-1: CLCx Simplified Block Diagram

    113
  • 19.1 CLCx Setup

    114
    • 19.1.1 Data Selection

      114
      • TABLE 19-1: CLCx Data Input Selection

        114
    • 19.1.2 Data Gating

      114
      • TABLE 19-2: Data gating Logic

        114
    • 19.1.3 Logic Function

      115
    • 19.1.4 Output Polarity

      115
    • 19.1.5 CLCx Setup Steps

      115
  • 19.2 CLCx Interrupts

    116
  • 19.3 Effects of a Reset

    116
  • 19.4 Operation During Sleep

    116
    • FIGURE 19-2: Input Data Selection and Gating

      117
    • FIGURE 19-3: Programmable Logic Functions

      118
  • 19.5 CLC Control Registers

    119
    • Register 19-1: CLCxCON: Configurable Logic CELL Control Register

      119
    • Register 19-2: CLCxPOL: Signal Polarity Control Register

      120
    • Register 19-3: CLCxSEL0: MULTIPLEXER DATA 1 and 2 SELECT Register

      121
    • Register 19-4: CLCxSEL1: MULTIPLEXER DATA 3 and 4 SELECT Register

      122
    • Register 19-5: CLCxGLS0: Gate 1 Logic Select Register

      123
    • Register 19-6: CLCxGLS1: Gate 2 Logic Select Register

      124
    • Register 19-7: CLCxGLS2: Gate 3 Logic Select Register

      125
    • Register 19-8: CLCxGLS3: Gate 4 Logic Select Register

      126
    • TABLE 19-3: Summary Of Registers Associated With CLCx

      127
• 20.0 Numerically Controlled Oscillator (NCO) Module

  129
  • FIGURE 20-1: Numerically Controlled Oscillator (NCOx) Module Simplified Block Diagram

    130
  • 20.1 NCOx OPERATION

    131
    • 20.1.1 NCOx CLOCK SOURCES

      131
    • 20.1.2 ACCUMULATOR

      131
    • 20.1.3 ADDER

      131
    • 20.1.4 INCREMENT REGISTERS

      131
      • EQUATION 20-1:

        131
  • 20.2 FIXED DUTY CYCLE (FDC) MODE

    132
  • 20.3 PULSE FREQUENCY (PF) MODE

    132
    • 20.3.1 OUTPUT PULSE WIDTH CONTROL

      132
  • 20.4 OUTPUT POLARITY CONTROL

    132
    • FIGURE 20-2: FDC Output Mode Operation Diagram

      133
  • 20.5 Interrupts

    134
  • 20.6 Effects of a Reset

    134
  • 20.7 Operation In Sleep

    134
  • 20.8 NCOx Control Registers

    135
    • Register 20-1: NCOxCON: NCOx Control Register

      135
    • Register 20-2: NCOxCLK: NCOx Input Clock Control Register

      135
    • Register 20-3: NCOxACCL: NCOx Accumulator Register – Low Byte

      136
    • Register 20-4: NCOxACCH: NCOx Accumulator Register – High Byte

      136
    • Register 20-5: NCOxACCU: NCOx Accumulator Register – Upper Byte

      136
    • Register 20-6: NCOxINCL: NCOx Increment Register – Low Byte

      137
    • Register 20-7: NCOxINCH: NCOx Increment Register – High Byte

      137
    • TABLE 20-1: Summary of Registers Associated with NCOx

      138
• 21.0 Complementary Waveform Generator (CWG) Module

  139
  • FIGURE 21-1: CWG Block Diagram

    140
  • FIGURE 21-2: Typical CWG Operation with PWM1 (no Auto-shutdown)

    141
  • 21.1 Fundamental Operation

    142
  • 21.2 Clock Source

    142
  • 21.3 Selectable Input Sources

    142
  • 21.4 Output Control

    142
    • 21.4.1 Output Enables

      142
    • 21.4.2 Polarity Control

      142
  • 21.5 Dead-Band Control

    142
  • 21.6 Rising Edge Dead Band

    142
  • 21.7 Falling Edge Dead Band

    143
  • 21.8 Dead-Band Uncertainty

    143
    • FIGURE 21-3: Dead-band Operation, CWGxDBR = 01H, CWGxDBF = 02H

      144
    • FIGURE 21-4: Dead-band Operation, CWGxDBR = 03H, CWGxDBF = 04H, Source shorter than dead band

      144
    • EQUATION 21-1: dead-band Delay time Uncertainty

      145
    • EXAMPLE 21-1: Dead-band Delay time Uncertainty

      145
  • 21.9 Auto-shutdown Control

    146
    • 21.9.1 SHUTDOWN

      146
  • 21.10 Operation During Sleep

    146
  • 21.11 Configuring the CWG

    147
    • 21.11.1 PIN OVERRIDE LEVELS

      147
    • 21.11.2 AUTO-SHUTDOWN RESTART

      147
      • FIGURE 21-5: SHUTDOWN Functionality, Auto-restart Disabled (GxARSEN = 0)

        148
      • FIGURE 21-6: SHUTDOWN Functionality, Auto-restart Enabled (GxARSEN = 1)

        148
  • 21.12 CWG Control Registers

    149
    • Register 21-1: CWGxCON0: CWG Control Register 0

      149
    • Register 21-2: CWGxCON1: CWG Control Register 1

      150
    • Register 21-3: CWGXCON2: CWG Control Register 2

      151
    • Register 21-4: CWGxDBR: Complementary Waveform Generator (CWGx) Rising Dead-band Count Register

      152
    • Register 21-5: CWGxdbf: Complementary Waveform Generator (CWGx) Falling Dead-band Count Register

      152
    • TABLE 21-1: Summary of Registers Associated with CWG

      153
• 22.0 In-Circuit Serial Programming™ (ICSP™)

  155
  • 22.1 High-Voltage Programming Entry Mode

    155
    • FIGURE 22-1: Vpp Limiter Example Circuit

      155
  • 22.2 Low-Voltage Programming Entry Mode

    156
  • 22.3 Common Programming Interfaces

    156
    • FIGURE 22-2: ICD RJ-11 Style Connector Interface

      156
    • FIGURE 22-3: PICkit™ Style Connector Interface

      156
    • FIGURE 22-4: Typical connection for ICSP™ programming

      157
• 23.0 Instruction Set Summary

  159
  • 23.1 Read-Modify-Write Operations

    159
    • TABLE 23-1: Opcode Field Descriptions

      159
    • FIGURE 23-1: General Format for Instructions

      159
    • TABLE 23-2: PIC10(L)F320/322 Instruction Set

      160
  • 23.2 Instruction Descriptions

    161
• 24.0 Electrical Specifications

  169
  • Absolute Maximum Ratings(†)

    169
    • FIGURE 24-1: PIC10F320/322 Voltage Frequency Graph, -40°C £ Ta £ +125°C

      170
    • FIGURE 24-2: PIC10LF320/322 Voltage Frequency Graph, -40°C £ Ta £ +125°C

      170
  • 24.1 DC Characteristics: PIC10(L)F320/322-I/E (Industrial, Extended)

    171
    • FIGURE 24-3: POR and POR Rearm with Slow Rising Vdd

      172
  • 24.2 DC Characteristics: PIC10(L)F320/322-I/E (Industrial, Extended)

    173
  • 24.3 DC Characteristics: PIC10(L)F320/322-I/E (Power-Down)

    175
  • 24.4 DC Characteristics: PIC10(L)F320/322-I/E

    176
  • 24.5 Memory Programming Requirements

    177
  • 24.6 Thermal Considerations

    178
  • 24.7 Timing Parameter Symbology

    179
    • FIGURE 24-4: Load Conditions

      179
  • 24.8 AC Characteristics: PIC10(L)F320/322-I/E

    180
    • FIGURE 24-5: Clock Timing

      180
    • TABLE 24-1: Clock Oscillator Timing Requirements

      180
    • TABLE 24-2: Oscillator Parameters

      180
    • FIGURE 24-6: CLKR and I/O Timing

      181
    • TABLE 24-3: CLKR and I/O Timing Parameters

      181
    • FIGURE 24-7: Reset, Watchdog Timer, and Power-up Timer Timing

      182
    • FIGURE 24-8: Brown-Out Reset Timing and Characteristics

      182
    • TABLE 24-4: Reset, Watchdog Timer, Power-up Timer and Brown-Out Reset Parameters

      183
    • FIGURE 24-9: Timer0 and Timer1 External Clock Timings

      183
    • TABLE 24-5: Timer0 External Clock Requirements

      183
    • TABLE 24-6: PIC10(L)F320/322 A/D Converter (ADC) Characteristics:

      184
    • TABLE 24-7: PIC10(L)F320/322 A/D Conversion Requirements

      184
    • FIGURE 24-10: PIC10(L)F320/322 A/D Conversion Timing (Normal Mode)

      185
    • FIGURE 24-11: PIC10(L)F320/322 A/D Conversion Timing (Sleep Mode)

      185
• 25.0 DC and AC Characteristics Graphs and Charts

  187
• 26.0 Development Support

  189
  • 26.1 MPLAB Integrated Development Environment Software

    189
  • 26.2 MPLAB C Compilers for Various Device Families

    190
  • 26.3 HI-TECH C for Various Device Families

    190
  • 26.4 MPASM Assembler

    190
  • 26.5 MPLINK Object Linker/ MPLIB Object Librarian

    190
  • 26.6 MPLAB Assembler, Linker and Librarian for Various Device Families

    190
  • 26.7 MPLAB SIM Software Simulator

    191
  • 26.8 MPLAB REAL ICE In-Circuit Emulator System

    191
  • 26.9 MPLAB ICD 3 In-Circuit Debugger System

    191
  • 26.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express

    191
  • 26.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express

    192
  • 26.12 MPLAB PM3 Device Programmer

    192
  • 26.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits

    192
• 27.0 Packaging Information

  193
  • 27.1 Package Marking Information

    193
    • TABLE 27-1: 8-Lead 2X3 dfn (mc) tOP Marking

      194
    • TABLE 27-2: 6-Lead SOT-23 (OT) Package Top Marking

      194
  • 27.2 Package Details

    195
• Appendix A: Data Sheet Revision History

  201
• INDEX

  203
  • A

    203
  • B

    203
  • C

    203
  • D

    203
  • E

    203
  • F

    203
  • G

    203
  • I

    204
  • L

    204
  • M

    204
  • N

    204
  • O

    204
  • P

    204
  • R

    205
  • S

    205
  • T

    205
  • V

    205
  • W

    205
• The Microchip Web Site

  207
• Customer Change Notification Service

  207
• Customer Support

  207
• Reader Response

  208
• Product Identification System

  209
• Worldwide Sales

  210