데이터 시트 (PIC10F322T-I/OT)차례High-Performance RISC CPU:3Special Microcontroller Features:3Low-Power Features (PIC10LF320/322):3Peripheral Features:3TABLE 1: PIC10(L)F320/322 Feature Summary4TABLE 2: 6 and 8-Pin Allocation Table (PIC10(L)F320/322)4Table of Contents5Most Current Data Sheet6Errata6Customer Notification System61.0 Device Overview7TABLE 1-1: Device Peripheral Summary7FIGURE 1-1: PIC10(L)F320/322 Block Diagram8TABLE 1-2: PIC10(L)F320/322 Pinout Description92.0 Memory Organization112.1 Program Memory Organization11TABLE 2-1: Device Sizes and Addresses11FIGURE 2-1: Program Memory Map And Stack For PIC10(L)F32012FIGURE 2-2: Program Memory Map And Stack For PIC10(L)F322122.2 Data Memory Organization132.2.1 General Purpose Register File132.2.2 Special Function Registers13Register 2-1: STATUS: STATUS Register152.2.3 Device Memory Maps16TABLE 2-2: PIC10(L)F320/322 Memory Map (Bank 0)16TABLE 2-3: Special Function Register Summary (Bank 0)172.3 PCL and PCLATH19FIGURE 2-3: Loading of PC in Different Situations192.3.1 Modifying PCL192.3.2 Stack192.4 Indirect Addressing, INDF and FSR Registers19EXAMPLE 2-1: Indirect Addressing19FIGURE 2-4: Direct/Indirect Addressing PIC10(L)F320/322203.0 Device Configuration213.1 Configuration Word21Register 3-1: CONFIG: Configuration Word223.2 Code Protection243.2.1 Program Memory Protection243.3 Write Protection243.4 User ID243.5 Device ID and Revision ID25Register 3-2: DEVICEID: Device ID Register(1)254.0 Oscillator Module274.1 Overview27FIGURE 4-1: PIC10(L)F320/322 Clock Source Block Diagram274.2 Clock Source Modes284.3 Internal Clock Modes284.3.1 INTOSC Mode284.3.2 Frequency Select Bits (IRCF)284.3.3 Reference Clock Output Control29Register 4-1: CLKRCON – Reference Clock Control Register294.4 Oscillator Control Registers304.4.1 Oscillator Control30Register 4-2: OSCCON: Oscillator Control Register304.5 External Clock Mode314.5.1 EC Mode31TABLE 4-1: Summary of Registers Associated with Clock Sources31TABLE 4-2: Summary of cONFIGURATION wORD with Clock Sources315.0 Resets33FIGURE 5-1: Simplified Block Diagram Of On-Chip Reset Circuit335.1 Power-on Reset (POR)345.1.1 Power-up Timer (PWRT)345.2 Brown-Out Reset (BOR)34TABLE 5-1: BOR Operating Modes345.2.1 BOR is Always On345.2.2 BOR is Off in Sleep345.2.3 BOR Controlled by Software34FIGURE 5-2: Brown-Out Situations35Register 5-1: BORCON: Brown-out Reset Control Register355.3 Low-Power Brown-out Reset (LPBOR)365.3.1 Enabling LPBOR365.4 MCLR36TABLE 5-2: MCLR Configuration365.4.1 MCLR Enabled365.4.2 MCLR Disabled365.5 Watchdog Timer (WDT) Reset365.6 Programming Mode ICSP Exit365.7 Power-Up Timer365.8 Start-up Sequence36FIGURE 5-3: Reset Start-Up Sequence375.9 Determining the Cause of a Reset38TABLE 5-3: Reset Status Bits and Their Significance38TABLE 5-4: Reset Condition for Special Registers385.10 Power Control (PCON) Register39Register 5-2: PCON: Power Control Register39TABLE 5-5: Summary Of Registers Associated With Resets39TABLE 5-6: Summary of cONFIGURATION wORD with Resets396.0 Interrupts41FIGURE 6-1: Interrupt Logic416.1 Operation426.2 Interrupt Latency42FIGURE 6-2: Interrupt Latency43FIGURE 6-3: INT Pin Interrupt Timing446.3 Interrupts During Sleep456.4 INT Pin456.5 Context Saving During Interrupts45EXAMPLE 6-1: Saving Status and W Registers in RAM456.6 Interrupt Control Registers466.6.1 INTCON Register46Register 6-1: INTCON: Interrupt Control Register466.6.2 PIE1 Register47Register 6-2: PIE1: Peripheral Interrupt Enable Register 1476.6.3 PIR1 Register48Register 6-3: PIR1: Peripheral Interrupt Request Register 148TABLE 6-1: Summary of Registers Associated with Interrupts497.0 Power-Down Mode (Sleep)517.1 Wake-up from Sleep517.1.1 Wake-up Using Interrupts52FIGURE 7-1: Wake-Up From Sleep Through Interrupt52TABLE 7-1: Summary of Registers Associated with pOWER-dOWN mODE528.0 Watchdog Timer53FIGURE 8-1: Watchdog Timer Block Diagram538.1 Independent Clock Source548.2 WDT Operating Modes548.2.1 WDT Is Always On548.2.2 WDT Is Off In Sleep548.2.3 WDT Controlled By Software54TABLE 8-1: WDT Operating Modes548.3 Time-Out Period548.4 Clearing the WDT548.5 Operation During Sleep54TABLE 8-2: WDT Clearing Conditions548.6 Watchdog Control Register55Register 8-1: WDTCON: Watchdog Timer Control Register55TABLE 8-3: Summary of Registers Associated with Watchdog Timer56TABLE 8-4: Summary of cONFIGURATION wORD with Watchdog Timer569.0 Flash Program Memory Control579.1 PMADRL and PMADRH Registers579.1.1 PMCON1 and PMCON2 Registers579.2 Flash Program Memory Overview57TABLE 9-1: Flash Memory Organization By Device589.2.1 Reading the Flash Program Memory58FIGURE 9-1: Flash Program Memory Read Flowchart58FIGURE 9-2: Flash Program Memory Read Cycle Execution59EXAMPLE 9-1: Flash PROGRAM MEMORY Read599.2.2 Flash Memory Unlock Sequence60FIGURE 9-3: Flash Program Memory Unlock Sequence Flowchart609.2.3 Erasing Flash Program Memory61FIGURE 9-4: Flash Program Memory Erase Flowchart61EXAMPLE 9-2: Erasing One Row of Program Memory629.2.4 Writing to Flash Program Memory63FIGURE 9-5: Block WRITES to Flash Program Memory With 16 write latches64FIGURE 9-6: Flash Program Memory Write Flowchart65EXAMPLE 9-3: Writing to Flash Program Memory669.3 Modifying Flash Program Memory67FIGURE 9-7: Flash Program Memory Modify Flowchart679.4 User ID, Device ID and Configuration Word Access68TABLE 9-2: User ID, Device ID and Configuration Word Access (cfgs = 1)68EXAMPLE 9-4: Configuration Word and Device ID Access689.5 Write Verify69FIGURE 9-8: Flash Program Memory Verify Flowchart699.6 Flash Program Memory Control Registers70Register 9-1: PMDATL: Program Memory Data Low70Register 9-2: PMDATH: Program Memory Data hIGH70Register 9-3: PMADRL: Program Memory Address Low71Register 9-4: PMADRH: Program Memory Address hIGH71Register 9-5: PMCON1: Program Memory Control 1 Register72Register 9-6: PMCON2: Program Memory Control 2 Register73TABLE 9-3: Summary of Registers Associated with Flash Program Memory73TABLE 9-4: Summary of cONFIGURATION wORD with Flash Program Memory7310.0 I/O Port75FIGURE 10-1: I/O Port Operation75EXAMPLE 10-1: Initializing PORTA7510.1 PORTA Registers7610.1.1 Weak Pull-ups7610.1.2 ANSELA Register7610.1.3 PORTA Functions and Output Priorities76TABLE 10-1: PORTA Output Priority76Register 10-1: PORTA: PORTA Register77Register 10-2: TRISA: PORTA Tri-State Register77Register 10-3: LATA: PORTA Data Latch Register78Register 10-4: ANSELA: PORTA Analog Select Register78Register 10-5: WPUA: Weak Pull-UP PORTA Register79TABLE 10-2: Summary of Registers Associated with PORTA8011.0 Interrupt-On-Change8111.1 Enabling the Module8111.2 Individual Pin Configuration8111.3 Interrupt Flags8111.4 Clearing Interrupt Flags81EXAMPLE 11-1:8111.5 Operation in Sleep81FIGURE 11-1: Interrupt-On-Change Block Diagram8211.6 Interrupt-On-Change Registers83Register 11-1: IOCAP: Interrupt-on-Change PORTA Positive Edge Register83Register 11-2: IOCAN: Interrupt-on-Change PORTA Negative Edge Register83Register 11-3: IOCAF: Interrupt-on-Change PORTA Flag Register84TABLE 11-1: Summary of Registers Associated with Interrupt-on-Change8412.0 Fixed Voltage Reference (FVR)8512.1 Independent Gain Amplifiers8512.2 FVR Stabilization Period85FIGURE 12-1: Voltage Reference Block Diagram85TABLE 12-1: Peripherals Requiring the Fixed Voltage Reference (FVR)8512.3 FVR Control Registers86Register 12-1: FVRCON: Fixed Voltage Reference Control Register86TABLE 12-2: Summary of Registers Associated with Fixed Voltage Reference8613.0 Internal Voltage Regulator (IVR)87TABLE 13-1: IVR Power modes - REGULATED87Register 13-1: VREGCON: Voltage Regulator Control Register8814.0 Temperature Indicator Module8914.1 Circuit Operation89EQUATION 14-1: Vout Ranges89FIGURE 14-1: Temperature Circuit Diagram8914.2 Minimum Operating Vdd vs. Minimum Sensing Temperature89TABLE 14-1: Recommended Vdd vs. Range8914.3 Temperature Output8914.4 ADC Acquisition Time89TABLE 14-2: Summary of Registers9015.0 Analog-to-Digital Converter (ADC) Module91FIGURE 15-1: ADC Simplified Block Diagram9115.1 ADC Configuration9215.1.1 Port Configuration9215.1.2 Channel Selection9215.1.3 ADC Voltage Reference9215.1.4 Conversion Clock92TABLE 15-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies93FIGURE 15-2: Analog-to-Digital Conversion Tad Cycles9315.1.5 Interrupts9415.2 ADC Operation9415.2.1 Starting a Conversion9415.2.2 Completion of a Conversion9415.2.3 Terminating a conversion9415.2.4 ADC Operation During Sleep9415.2.5 A/D Conversion Procedure9515.3 ADC Register Definitions96Register 15-1: ADCON: A/D Control Register 096Register 15-2: ADRES: ADC Result Register9715.4 A/D Acquisition Requirements98EQUATION 15-1: Acquisition Time Example98FIGURE 15-3: Analog Input Model99FIGURE 15-4: ADC Transfer Function99TABLE 15-2: Summary of Registers Associated with ADC10016.0 Timer0 Module10116.1 Timer0 Operation10116.1.1 8-bit Timer Mode10116.1.2 8-Bit Counter Mode101FIGURE 16-1: Block Diagram of the Timer0 Prescaler10116.1.3 Software Programmable Prescaler10216.1.4 Timer0 Interrupt10216.1.5 8-BIT Counter Mode Synchronization102Register 16-1: OPTION_REG: OPTION Register103TABLE 16-1: Summary of Registers Associated with Timer010317.0 Timer2 Module10517.1 Timer2 Operation105FIGURE 17-1: Timer2 Block Diagram105Register 17-1: T2CON: Timer2 Control Register106TABLE 17-1: Summary of Registers Associated With Timer210618.0 Pulse-Width Modulation (PWM) Module107FIGURE 18-1: Simplified PWM Block Diagram107FIGURE 18-2: PWM Output10718.1 PWMx Pin Configuration10818.1.1 Fundamental Operation10818.1.2 PWM OUTPUT Polarity10818.1.3 PWM period108EQUATION 18-1: PWM Period10818.1.4 PWM Duty Cycle108EQUATION 18-2: Pulse Width108EQUATION 18-3: Duty Cycle Ratio10818.1.5 PWM Resolution109EQUATION 18-4: PWM Resolution109TABLE 18-1: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)109TABLE 18-2: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)10918.1.6 Operation in Sleep Mode10918.1.7 Changes in System Clock Frequency10918.1.8 Effects of Reset10918.1.9 Setup for PWM Operation using PWMx Pins11018.2 PWM Register Definitions111Register 18-1: PWMxCON: PWM Control Register111Register 18-2: PWMXDCH: PWM Duty Cycle High Bits112Register 18-3: PWMxDCL: PWM Duty Cycle LOW Bits112TABLE 18-3: Summary of Registers Associated with PWM11219.0 Configurable Logic Cell (CLC)113FIGURE 19-1: CLCx Simplified Block Diagram11319.1 CLCx Setup11419.1.1 Data Selection114TABLE 19-1: CLCx Data Input Selection11419.1.2 Data Gating114TABLE 19-2: Data gating Logic11419.1.3 Logic Function11519.1.4 Output Polarity11519.1.5 CLCx Setup Steps11519.2 CLCx Interrupts11619.3 Effects of a Reset11619.4 Operation During Sleep116FIGURE 19-2: Input Data Selection and Gating117FIGURE 19-3: Programmable Logic Functions11819.5 CLC Control Registers119Register 19-1: CLCxCON: Configurable Logic CELL Control Register119Register 19-2: CLCxPOL: Signal Polarity Control Register120Register 19-3: CLCxSEL0: MULTIPLEXER DATA 1 and 2 SELECT Register121Register 19-4: CLCxSEL1: MULTIPLEXER DATA 3 and 4 SELECT Register122Register 19-5: CLCxGLS0: Gate 1 Logic Select Register123Register 19-6: CLCxGLS1: Gate 2 Logic Select Register124Register 19-7: CLCxGLS2: Gate 3 Logic Select Register125Register 19-8: CLCxGLS3: Gate 4 Logic Select Register126TABLE 19-3: Summary Of Registers Associated With CLCx12720.0 Numerically Controlled Oscillator (NCO) Module129FIGURE 20-1: Numerically Controlled Oscillator (NCOx) Module Simplified Block Diagram13020.1 NCOx OPERATION13120.1.1 NCOx CLOCK SOURCES13120.1.2 ACCUMULATOR13120.1.3 ADDER13120.1.4 INCREMENT REGISTERS131EQUATION 20-1:13120.2 FIXED DUTY CYCLE (FDC) MODE13220.3 PULSE FREQUENCY (PF) MODE13220.3.1 OUTPUT PULSE WIDTH CONTROL13220.4 OUTPUT POLARITY CONTROL132FIGURE 20-2: FDC Output Mode Operation Diagram13320.5 Interrupts13420.6 Effects of a Reset13420.7 Operation In Sleep13420.8 NCOx Control Registers135Register 20-1: NCOxCON: NCOx Control Register135Register 20-2: NCOxCLK: NCOx Input Clock Control Register135Register 20-3: NCOxACCL: NCOx Accumulator Register – Low Byte136Register 20-4: NCOxACCH: NCOx Accumulator Register – High Byte136Register 20-5: NCOxACCU: NCOx Accumulator Register – Upper Byte136Register 20-6: NCOxINCL: NCOx Increment Register – Low Byte137Register 20-7: NCOxINCH: NCOx Increment Register – High Byte137TABLE 20-1: Summary of Registers Associated with NCOx13821.0 Complementary Waveform Generator (CWG) Module139FIGURE 21-1: CWG Block Diagram140FIGURE 21-2: Typical CWG Operation with PWM1 (no Auto-shutdown)14121.1 Fundamental Operation14221.2 Clock Source14221.3 Selectable Input Sources14221.4 Output Control14221.4.1 Output Enables14221.4.2 Polarity Control14221.5 Dead-Band Control14221.6 Rising Edge Dead Band14221.7 Falling Edge Dead Band14321.8 Dead-Band Uncertainty143FIGURE 21-3: Dead-band Operation, CWGxDBR = 01H, CWGxDBF = 02H144FIGURE 21-4: Dead-band Operation, CWGxDBR = 03H, CWGxDBF = 04H, Source shorter than dead band144EQUATION 21-1: dead-band Delay time Uncertainty145EXAMPLE 21-1: Dead-band Delay time Uncertainty14521.9 Auto-shutdown Control14621.9.1 SHUTDOWN14621.10 Operation During Sleep14621.11 Configuring the CWG14721.11.1 PIN OVERRIDE LEVELS14721.11.2 AUTO-SHUTDOWN RESTART147FIGURE 21-5: SHUTDOWN Functionality, Auto-restart Disabled (GxARSEN = 0)148FIGURE 21-6: SHUTDOWN Functionality, Auto-restart Enabled (GxARSEN = 1)14821.12 CWG Control Registers149Register 21-1: CWGxCON0: CWG Control Register 0149Register 21-2: CWGxCON1: CWG Control Register 1150Register 21-3: CWGXCON2: CWG Control Register 2151Register 21-4: CWGxDBR: Complementary Waveform Generator (CWGx) Rising Dead-band Count Register152Register 21-5: CWGxdbf: Complementary Waveform Generator (CWGx) Falling Dead-band Count Register152TABLE 21-1: Summary of Registers Associated with CWG15322.0 In-Circuit Serial Programming™ (ICSP™)15522.1 High-Voltage Programming Entry Mode155FIGURE 22-1: Vpp Limiter Example Circuit15522.2 Low-Voltage Programming Entry Mode15622.3 Common Programming Interfaces156FIGURE 22-2: ICD RJ-11 Style Connector Interface156FIGURE 22-3: PICkit™ Style Connector Interface156FIGURE 22-4: Typical connection for ICSP™ programming15723.0 Instruction Set Summary15923.1 Read-Modify-Write Operations159TABLE 23-1: Opcode Field Descriptions159FIGURE 23-1: General Format for Instructions159TABLE 23-2: PIC10(L)F320/322 Instruction Set16023.2 Instruction Descriptions16124.0 Electrical Specifications169Absolute Maximum Ratings(†)169FIGURE 24-1: PIC10F320/322 Voltage Frequency Graph, -40°C £ Ta £ +125°C170FIGURE 24-2: PIC10LF320/322 Voltage Frequency Graph, -40°C £ Ta £ +125°C17024.1 DC Characteristics: PIC10(L)F320/322-I/E (Industrial, Extended)171FIGURE 24-3: POR and POR Rearm with Slow Rising Vdd17224.2 DC Characteristics: PIC10(L)F320/322-I/E (Industrial, Extended)17324.3 DC Characteristics: PIC10(L)F320/322-I/E (Power-Down)17524.4 DC Characteristics: PIC10(L)F320/322-I/E17624.5 Memory Programming Requirements17724.6 Thermal Considerations17824.7 Timing Parameter Symbology179FIGURE 24-4: Load Conditions17924.8 AC Characteristics: PIC10(L)F320/322-I/E180FIGURE 24-5: Clock Timing180TABLE 24-1: Clock Oscillator Timing Requirements180TABLE 24-2: Oscillator Parameters180FIGURE 24-6: CLKR and I/O Timing181TABLE 24-3: CLKR and I/O Timing Parameters181FIGURE 24-7: Reset, Watchdog Timer, and Power-up Timer Timing182FIGURE 24-8: Brown-Out Reset Timing and Characteristics182TABLE 24-4: Reset, Watchdog Timer, Power-up Timer and Brown-Out Reset Parameters183FIGURE 24-9: Timer0 and Timer1 External Clock Timings183TABLE 24-5: Timer0 External Clock Requirements183TABLE 24-6: PIC10(L)F320/322 A/D Converter (ADC) Characteristics:184TABLE 24-7: PIC10(L)F320/322 A/D Conversion Requirements184FIGURE 24-10: PIC10(L)F320/322 A/D Conversion Timing (Normal Mode)185FIGURE 24-11: PIC10(L)F320/322 A/D Conversion Timing (Sleep Mode)18525.0 DC and AC Characteristics Graphs and Charts18726.0 Development Support18926.1 MPLAB Integrated Development Environment Software18926.2 MPLAB C Compilers for Various Device Families19026.3 HI-TECH C for Various Device Families19026.4 MPASM Assembler19026.5 MPLINK Object Linker/ MPLIB Object Librarian19026.6 MPLAB Assembler, Linker and Librarian for Various Device Families19026.7 MPLAB SIM Software Simulator19126.8 MPLAB REAL ICE In-Circuit Emulator System19126.9 MPLAB ICD 3 In-Circuit Debugger System19126.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express19126.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express19226.12 MPLAB PM3 Device Programmer19226.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits19227.0 Packaging Information19327.1 Package Marking Information193TABLE 27-1: 8-Lead 2X3 dfn (mc) tOP Marking194TABLE 27-2: 6-Lead SOT-23 (OT) Package Top Marking19427.2 Package Details195Appendix A: Data Sheet Revision History201INDEX203A203B203C203D203E203F203G203I204L204M204N204O204P204R205S205T205V205W205The Microchip Web Site207Customer Change Notification Service207Customer Support207Reader Response208Product Identification System209Worldwide Sales210크기: 1.54메가바이트페이지: 210Language: English매뉴얼 열기