User ManualTable of ContentsTitle Page1Contact Information2Table of Contents3List of Figures15List of Tables19List of Examples25About This Book27Chapter1 Introduction311.1 Features of the MC68VZ328321.2 CPU341.2.1 CPU Programming Model351.2.2 Data and Address Mode Types361.2.3 FLX68000 Instruction Set361.3 Modules of the MC68VZ328381.3.1 Memory Controller381.3.2 Clock Generation Module and Power Control Module381.3.3 System Control391.3.4 Chip-Select Logic391.3.5 DRAM Controller391.3.6 LCD Controller391.3.7 Interrupt Controller391.3.8 General-Purpose I/O (GPIO) Lines401.3.9 Real-Time Clock401.3.10 General-Purpose Timer401.3.11 Serial Peripheral Interfaces (SPI)401.3.12 Universal Asynchronous Receiver/Transmitter (UART) Modules401.3.13 Pulse-Width Modulators (PWM)411.3.14 In-Circuit Emulation Module411.3.15 Bootstrap Mode41Chapter2 Signal Descriptions432.1 Signals Grouped by Function442.2 Power and Ground Signals462.3 Clock and System Control Signals462.4 Address Bus Signals472.5 Data Bus Signals472.6 Bus Control Signals482.7 Interrupt Controller Signals482.8 LCD Controller Signals492.9 UART 1 and UART 2 Controller Signals502.10 Timer Signals502.11 Pulse-Width Modulator Signals512.12 Serial Peripheral Interface 1 Signals512.13 Serial Peripheral Interface 2 Signals512.14 Chip-Select and EDO RAM Interface Signals522.15 SDRAM Interface Signals522.16 In-Circuit Emulation (ICE) Signals53Chapter3 Memory Map553.1 Programmer’s Memory Map56Chapter4 Clock Generation Module and Power Control Module694.1 Introduction to the Clock Generation Module704.2 CGM Operational Overview714.3 Detailed CGM Clock Descriptions724.3.1 CLK32 Clock Signal724.3.2 PLLCLK Clock Signal724.3.2.1 PLLCLK Initial Power-up Sequence734.3.2.2 PLL Frequency Selection744.3.2.3 PLLCLK Frequency Selection Programming Example744.3.2.4 Programming Considerations When Changing Frequencies754.4 CGM Programming Model764.4.1 PLL Control Register764.4.2 PLL Frequency Select Register784.5 Introduction to the Power Control Module784.5.1 Operating the PCM794.5.1.1 Normal Mode794.5.1.2 Burst Mode794.5.1.3 Doze Mode794.5.1.4 Sleep Mode804.5.2 CGM Operation During Sleep Mode804.5.3 Burst Mode Operation804.5.4 Power Control Register82Chapter5 System Control835.1 System Control Operation835.1.1 Bus Monitors and Watchdog Timers835.2 Programming Model845.2.1 System Control Register845.2.2 Peripheral Control Register865.2.3 ID Register875.2.4 I/O Drive Control Register88Chapter6 Chip-Select Logic896.1 Overview of the CSL896.2 Chip-Select Operation906.2.1 Memory Protection906.2.2 Programmable Data Bus Size916.2.3 Overlapping Chip-Select Registers926.3 Programming Model926.3.1 Chip-Select Group Base Address Registers926.3.2 Chip-Select Upper Group Base Address Register946.3.3 Chip-Select Registers966.3.4 Emulation Chip-Select Register1046.3.5 Chip-Select Control Register 11046.3.6 Chip-Select Control Register 21066.3.7 Chip-Select Control Register 3108Chapter7 DRAM Controller1117.1 Introduction to the DRAM Controller1117.2 DRAM Controller Operation1137.2.1 Address Multiplexing1137.2.2 DTACK Generation1177.2.3 Refresh Control1177.2.4 LCD Interface1187.2.5 8-Bit Mode1197.2.6 Low-Power Standby Mode1197.2.7 Data Retention During Reset1207.2.8 Data Retention Sequence1217.3 Programming Model1227.3.1 DRAM Memory Configuration Register1227.3.2 DRAM Control Register1247.3.3 SDRAM Control Register1267.3.4 SDRAM Power-down Register128Chapter8 LCD Controller1298.1 LCD Controller Features1298.2 LCD Controller Operation1308.2.1 Connecting the LCD Controller to an LCD Panel1318.2.1.1 Panel Interface Timing1318.2.2 Controlling the Display1328.2.2.1 Format of the LCD Screen1328.2.2.2 Format of the Cursor1338.2.2.3 Mapping the Display Data1348.2.2.4 Generating Grayscale Tones1348.2.3 Using Low-Power Mode1368.2.4 Using the DMA Controller1368.2.4.1 Bus Bandwidth Calculation Example1368.2.5 Self-Refresh Mode1378.2.5.1 Entering Self-Refresh Mode1378.2.5.2 Canceling Self-Refresh Mode1378.3 Programming Model1388.3.1 LCD Screen Starting Address Register1388.3.2 LCD Virtual Page Width Register1398.3.3 LCD Screen Width Register1398.3.4 LCD Screen Height Register1408.3.5 LCD Cursor X Position Register1408.3.6 LCD Cursor Y Position Register1418.3.7 LCD Cursor Width and Height Register1428.3.8 LCD Blink Control Register1428.3.9 LCD Panel Interface Configuration Register1438.3.10 LCD Polarity Configuration Register1448.3.11 LACD Rate Control Register1448.3.12 LCD Pixel Clock Divider Register1458.3.13 LCD Clocking Control Register1468.3.14 LCD Refresh Rate Adjustment Register1468.3.15 LCD Panning Offset Register1478.3.16 LCD Frame Rate Control Modulation Register1478.3.17 LCD Gray Palette Mapping Register1488.3.18 PWM Contrast Control Register1488.3.19 Refresh Mode Control Register1498.3.20 DMA Control Register1508.4 Programming Example150Chapter9 Interrupt Controller1519.1 Interrupt Processing1529.2 Exception Vectors1539.3 Reset1549.3.1 Operation Mode Selection During Reset1559.3.2 Data Bus Width for Boot Device Operation1559.4 Interrupt Controller Operation1559.4.1 Interrupt Priority Processing1559.4.2 Interrupt Vectors1569.5 Vector Generation1569.6 Programming Model1579.6.1 Interrupt Vector Register1579.6.2 Interrupt Control Register1589.6.3 Interrupt Mask Register1609.6.4 Interrupt Status Register1629.6.5 Interrupt Pending Register1669.6.6 Interrupt Level Register1699.7 Keyboard Interrupts1709.8 Pen Interrupts170Chapter10 I/O Ports17110.1 Port Configuration17110.2 Status of I/O Ports During Reset17210.2.1 Warm Reset17210.2.2 Power-up Reset17310.2.3 Summary of Port Behavior During Reset17410.3 I/O Port Operation17410.3.1 Data Flow from the I/O Module17410.3.2 Data Flow to the I/O Module17510.3.3 Operating a Port as GPIO17510.3.4 Port Pull-up and Pull-down Resistors17610.4 Programming Model17610.4.1 Port A Registers17610.4.1.1 Port A Direction Register17710.4.1.2 Port A Data Register17710.4.1.3 Port A Pull-up Enable Register17810.4.2 Port B Registers17810.4.2.1 Port B Direction Register17810.4.2.2 Port B Data Register17910.4.2.3 Port B Dedicated I/O Functions18010.4.2.4 Port B Pull-up Enable Register18010.4.2.5 Port B Select Register18110.4.3 Port C Registers18110.4.3.1 Port C Direction Register18210.4.3.2 Port C Data Register18210.4.3.3 Port C Dedicated I/O Functions18310.4.3.4 Port C Pull-down Enable Register18310.4.3.5 Port C Select Register18410.4.4 Port D Operation18510.4.5 Port D Registers18610.4.5.1 Port D Direction Register18610.4.5.2 Port D Data Register18710.4.5.3 Port D Interrupt Options18810.4.5.4 Port D Pull-up Enable Register18810.4.5.5 Port D Select Register18910.4.5.6 Port D Polarity Register18910.4.5.7 Port D Interrupt Request Enable Register19010.4.5.8 Port D Keyboard Enable Register19010.4.5.9 Port D Interrupt Request Edge Register19010.4.6 Port E Registers19110.4.6.1 Port E Direction Register19110.4.6.2 Port E Data Register19210.4.6.3 Port E Dedicated I/O Functions19210.4.6.4 Port E Pull-up Enable Register19310.4.6.5 Port E Select Register19310.4.7 Port F Registers19410.4.7.1 Port F Direction Register19410.4.7.2 Port F Data Register19510.4.7.3 Port F Dedicated I/O Functions19610.4.7.4 Port F Pull-up/Pull-down Enable Register19710.4.7.5 Port F Select Register19710.4.8 Port G Registers19810.4.8.1 Port G Direction Register19810.4.8.2 Port G Data Register19810.4.8.3 Port G Dedicated I/O Functions19910.4.8.4 Port G Operational Considerations20010.4.8.5 Port G Pull-up Enable Register20010.4.8.6 Port G Select Register20010.4.9 Port J Registers20110.4.9.1 Port J Direction Register20110.4.9.2 Port J Data Register20210.4.9.3 Port J Dedicated I/O Functions20210.4.9.4 Port J Pull-up Enable Register20310.4.9.5 Port J Select Register20310.4.10 Port K Registers20410.4.10.1 Port K Direction Register20410.4.10.2 Port K Data Register20410.4.10.3 Port K Dedicated I/O Functions20510.4.10.4 Port K Pull-up/Pull-down Enable Register20610.4.10.5 Port K Select Register20610.4.11 Port M Registers20710.4.11.1 Port M Direction Register20710.4.11.2 Port M Data Register20810.4.11.3 Port M Dedicated I/O Functions20910.4.11.4 Port M Pull-up/Pull-down Enable Register20910.4.11.5 Port M Select Register210Chapter11 Real-Time Clock21111.1 RTC Overview21211.1.1 Prescaler21211.1.2 Time-of-Day Counter21311.1.3 Alarm21311.1.4 Watchdog Timer21411.1.5 Real-Time Interrupt Timer21411.1.6 Minute Stopwatch21411.1.6.1 Minute Stopwatch Application Example21411.2 Programming Model21511.2.1 RTC Time Register21511.2.2 RTC Day Count Register21611.2.3 RTC Alarm Register21711.2.4 RTC Day Alarm Register21811.2.5 Watchdog Timer Register21911.2.6 RTC Control Register22011.2.7 RTC Interrupt Status Register22011.2.8 RTC Interrupt Enable Register22211.2.9 Stopwatch Minutes Register224Chapter12 General-Purpose Timers22512.1 GP Timer Overview22512.1.1 Clock Source and Prescaler22612.1.2 Timer Events and Modes of Operation22612.1.2.1 Restart Mode22612.1.2.2 Free-Running Mode22612.1.3 Timer Capture Register22712.1.4 TOUT/TIN/PB6 Pin22712.1.5 Cascaded Timers22812.1.5.1 Compare and Capture Using Cascaded Timers22812.2 Programming Model23012.2.1 Timer Control Registers 1 and 223012.2.2 Timer Prescaler Registers 1 and 223212.2.3 Timer Compare Registers 1 and 223312.2.4 Timer Capture Registers 1 and 223412.2.5 Timer Counter Registers 1 and 223512.2.6 Timer Status Registers 1 and 2236Chapter13 Serial Peripheral Interface 1 and 223713.1 SPI 1 Overview23713.2 SPI 1 Operation23813.2.1 Using SPI 1 as Master23813.2.2 Using SPI 1 as Slave23813.2.3 SPI 1 Phase and Polarity Configurations23913.2.4 SPI 1 Signals23913.3 SPI 1 Programming Model24013.3.1 SPI 1 Receive Data Register24013.3.2 SPI 1 Transmit Data Register24113.3.3 SPI 1 Control/Status Register24213.3.4 SPI 1 Interrupt Control/Status Register24413.3.5 SPI 1 Test Register24613.3.6 SPI 1 Sample Period Control Register24613.4 SPI 2 Overview24713.5 SPI 2 Operation24813.5.1 SPI 2 Phase and Polarity Configurations24913.5.2 SPI 2 Signals24913.6 SPI 2 Programming Model25013.6.1 SPI 2 Data Register25013.6.2 SPI 2 Data Register Timing25013.6.3 SPI 2 Control/Status Register251Chapter14 Universal Asynchronous Receiver/Transmitter 1 and 225314.1 Introduction to the UARTs25314.2 Serial Operation25414.2.1 NRZ Mode25414.2.2 IrDA Mode25514.2.3 Serial Interface Signals25514.3 UART Operation25614.3.1 Transmitter Operation25614.3.1.1 TxFIFO Buffer Operation25614.3.1.2 CTS Signal Operation25714.3.2 Receiver Operation25814.3.2.1 Rx FIFO Buffer Operation25814.3.3 Baud Rate Generator Operation25814.3.3.1 Divider25914.3.3.2 Non-Integer Prescaler25914.3.3.3 Integer Prescaler26114.4 Programming Model26214.4.1 UART 1 Status/Control Register26214.4.2 UART 1 Baud Control Register26414.4.3 UART 1 Receiver Register26514.4.4 UART 1 Transmitter Register26614.4.5 UART 1 Miscellaneous Register26814.4.6 UART 1 Non-Integer Prescaler Register27014.4.7 Non-Integer Prescaler Programming Example27114.4.8 UART 2 Status/Control Register27214.4.9 UART 2 Baud Control Register27414.4.10 UART 2 Receiver Register27514.4.11 UART 2 Transmitter Register27614.4.12 UART 2 Miscellaneous Register27814.4.13 UART 2 Non-Integer Prescaler Register28014.4.14 FIFO Level Marker Interrupt Register281Chapter15 Pulse-Width Modulator 1 and 228315.1 Introduction to PWM Operation28315.1.1 PWM Clock Signals28415.2 PWM 128415.3 PWM Operation28515.3.1 Playback Mode28515.3.1.1 Tone Mode28515.3.1.2 D/A Mode28515.4 Programming Model28615.4.1 PWM 1 Control Register28615.4.2 PWM 1 Sample Register28815.4.3 PWM 1 Period Register28915.4.4 PWM 1 Counter Register28915.5 PWM 229015.5.1 PWM 2 Control Register29015.5.2 PWM 2 Period Register29115.5.3 PWM 2 Pulse Width Register29215.5.4 PWM 2 Counter Register292Chapter16 In-Circuit Emulation29316.1 ICE Operation29416.1.1 Entering Emulation Mode29416.1.2 Detecting Breakpoints29416.1.2.1 Execution Breakpoints vs. Bus Breakpoints29516.1.3 Using the Signal Decoder29516.1.4 Using the Interrupt Gate Module29516.1.5 Using the A-Line Insertion Unit29516.2 Programming Model29616.2.1 In-Circuit Emulation Module Address Compare and Mask Registers29616.2.2 In-Circuit Emulation Module Control Compare and Mask Register29816.2.3 In-Circuit Emulation Module Control Register30016.2.4 In-Circuit Emulation Module Status Register30216.3 Typical Design Programming Example30216.3.1 Host Interface30316.3.2 Dedicated Debug Monitor Memory30316.3.3 Emulation Memory Mapping FPGA and Emulation Memory30416.3.4 Optional Extra Hardware Breakpoint30416.3.5 Optional Trace Module30416.4 Plug-in Emulator Design Example30416.5 Application Development Design Example306Chapter17 Bootstrap Mode30717.1 Bootstrap Mode Operation30717.1.1 Entering Bootstrap Mode30817.1.2 Bootstrap Record Format30817.1.2.1 Data B-Record Format30817.1.2.2 Execution B-Record Format30817.1.3 Setting Up the RS-232 Terminal30917.1.4 Changing the Speed of Communication30917.1.5 System Initialization Programming Example31017.1.6 Application Programming Example31117.1.7 Example of Instruction Buffer Usage31217.2 Bootloader Flowchart31217.3 Special Notes314Chapter18 Application Guide31518.1 Design Checklist31518.1.1 Determining the Chip ID and Version31518.1.2 8-Bit Bus Width Issues31518.1.3 Clock and Layout Considerations31618.1.4 Bus and I/O Considerations316Chapter19 Electrical Characteristics31719.1 Maximum Ratings31719.2 DC Electrical Characteristics31819.3 AC Electrical Characteristics31819.3.1 CLKO Reference to Chip-Select Signals Timing31819.3.2 Chip-Select Read Cycle Timing31919.3.3 Chip-Select Write Cycle Timing32119.3.4 Chip-Select Flash Write Cycle Timing32219.3.5 Chip-Select Timing Trim32419.3.6 DRAM Read Cycle 16-Bit Access (CPU Bus Master)32419.3.7 DRAM Write Cycle 16-Bit Access (CPU Bus Master)32619.3.8 DRAM Hidden Refresh Cycle (Normal Mode)32719.3.9 DRAM Hidden Refresh Cycle (Low-Power Mode)32819.3.10 LCD SRAM/ROM DMA Cycle 16-Bit Mode Access (1 Wait State)32919.3.11 LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master)33019.3.12 LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master)33219.3.13 LCD Controller Timing33319.3.14 Page-Miss SDRAM CPU Read Cycle (CAS Latency=1)33519.3.15 Page-Hit SDRAM CPU Read Cycle (CAS Latency=1)33619.3.16 Page-Hit CPU Read Cycle for 8-Bit SDRAM (CAS Latency=1)33719.3.17 Page-Miss SDRAM CPU Write Cycle (CAS Latency=1)33819.3.18 Page-Hit SDRAM CPU Write Cycle (CAS Latency=1)33919.3.19 Page-Hit CPU Byte-Write Cycle for 8-Bit SDRAM (CAS Latency=1)34019.3.20 Page-Hit CPU Read Cycle in Power-down Mode (CAS Latency=1, Bit APEN of SDRAM Power-down...34119.3.21 Exit Self-Refresh Due to CPU Read Cycle (CAS Latency=1, Bit RM of DRAM Control Register...34219.3.22 Enter Self-Refresh Due to No Activity for 64 Clocks (Bit RM of DRAM Control Register=1)34319.3.23 Page-Miss at Starting of LCD DMA for SDRAM (CAS Latency=1)34419.3.24 Page-Miss at Start and in Middle of LCD DMA (CAS Latency=1)34519.3.25 Page-Hit LCD DMA Cycle for SDRAM (CAS Latency=1)34619.3.26 SPI 1 and SPI 2 Generic Timing34819.3.27 SPI 1 Master Using DATA_READY Edge Trigger34819.3.28 SPI 1 Master Using DATA_READY Level Trigger34919.3.29 SPI 1 Master “Don’t Care” DATA_READY34919.3.30 SPI 1 Slave FIFO Advanced by Bit Count34919.3.31 SPI 1 Slave FIFO Advanced by SS Rising Edge35019.3.32 Normal Mode Timing35119.3.33 Emulation Mode Timing35119.3.34 Bootstrap Mode Timing352Chapter20 Mechanical Data and Ordering Information35320.1 Ordering Information35320.2 TQFP Pin Assignments35420.3 TQFP Package Dimensions35520.4 MAPBGA Pin Assignments35620.5 MAPBGA Package Dimensions35720.6 PCB Finish Requirement358Index359Size: 4.95 MBPages: 376Language: EnglishOpen manual
