Texas Instruments TMS320C642x DSP User Manuals

Table of Contents

• Table of Contents

  3
• Preface

  6
• 1 Introduction

  7
  • 1.1 Purpose of the Peripheral

    7
  • 1.2 Features

    7
  • 1.3 Functional Block Diagram

    8
  • 1.4 Supported Use Case Statement

    8
  • 1.5 Industry Standard(s) Compliance Statement

    8
• 2 Peripheral Architecture

  9
  • 2.1 Clock Control

    9
    • 2.1.1 Clock Source

      9
    • 2.1.2 Clock Configuration

      10
    • 2.1.3 DDR2 Memory Controller Internal Clock Domains

      10
  • 2.2 Memory Map

    10
  • 2.3 Signal Descriptions

    11
  • 2.4 Protocol Description(s)

    12
    • 2.4.1 Refresh Mode

      13
    • 2.4.2 Deactivation (DCAB and DEAC)

      14
    • 2.4.3 Activation (ACTV)

      16
    • 2.4.4 READ Command

      17
    • 2.4.5 Write (WRT) Command

      18
    • 2.4.6 Mode Register Set (MRS and EMRS)

      19
  • 2.5 Memory Width and Byte Alignment

    20
  • 2.6 Endianness Support

    21
  • 2.7 Address Mapping

    22
  • 2.8 DDR2 Memory Controller Interface

    26
    • 2.8.1 Command Ordering and Scheduling, Advanced Concept

      27
    • 2.8.2 Command Starvation

      28
    • 2.8.3 Possible Race Condition

      28
  • 2.9 Refresh Scheduling

    29
  • 2.10 Self-Refresh Mode

    29
  • 2.11 Reset Considerations

    30
  • 2.12 VTP IO Buffer Calibration

    31
  • 2.13 Auto-Initialization Sequence

    31
    • 2.13.1 Initializing Configuration Registers

      32
    • 2.13.2 Initializing Following Device Power Up and Device RESET

      33
  • 2.14 Interrupt Support

    34
  • 2.15 DMA Event Support

    34
  • 2.16 Power Management

    34
    • 2.16.1 DDR2 Memory Controller Clock Stop Procedure

      35
  • 2.17 Emulation Considerations

    35
• 3 Supported Use Cases

  36
  • 3.1 Connecting the DDR2 Memory Controller to DDR2 Memory

    36
  • 3.2 Configuring Memory-Mapped Registers to Meet DDR2-400 Specification

    36
    • 3.2.1 Configuring SDRAM Bank Configuration Register (SDBCR)

      38
    • 3.2.2 Configuring SDRAM Refresh Control Register (SDRCR)

      38
    • 3.2.3 Configuring SDRAM Timing Registers (SDTIMR and SDTIMR2)

      39
    • 3.2.4 Configuring DDR PHY Control Register (DDRPHYCR)

      40
• 4 DDR2 Memory Controller Registers

  41
  • 4.1 SDRAM Status Register (SDRSTAT)

    42
  • 4.2 SDRAM Bank Configuration Register (SDBCR)

    43
  • 4.3 SDRAM Refresh Control Register (SDRCR)

    45
  • 4.4 SDRAM Timing Register (SDTIMR)

    46
  • 4.5 SDRAM Timing Register 2 (SDTIMR2)

    47
  • 4.6 Peripheral Bus Burst Priority Register (PBBPR)

    48
  • 4.7 Interrupt Raw Register (IRR)

    49
  • 4.8 Interrupt Masked Register (IMR)

    50
  • 4.9 Interrupt Mask Set Register (IMSR)

    51
  • 4.10 Interrupt Mask Clear Register (IMCR)

    52
  • 4.11 DDR PHY Control Register (DDRPHYCR)

    53
  • 4.12 VTP IO Control Register (VTPIOCR)

    54
  • 4.13 DDR VTP Register (DDRVTPR)

    55
  • 4.14 DDR VTP Enable Register (DDRVTPER)

    55
• Appendix A Revision History

  56