用户手册 — Texas Instruments TMS320C642x DSP

目录

• Table of Contents

  3
• Preface

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• 1 Introduction

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  • 1.1 Purpose of the Peripheral

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  • 1.2 Features

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  • 1.3 Functional Block Diagram

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  • 1.4 Supported Use Case Statement

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  • 1.5 Industry Standard(s) Compliance Statement

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• 2 Peripheral Architecture

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  • 2.1 Clock Control

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    • 2.1.1 Clock Source

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    • 2.1.2 Clock Configuration

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    • 2.1.3 DDR2 Memory Controller Internal Clock Domains

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  • 2.2 Memory Map

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  • 2.3 Signal Descriptions

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  • 2.4 Protocol Description(s)

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    • 2.4.1 Refresh Mode

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    • 2.4.2 Deactivation (DCAB and DEAC)

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    • 2.4.3 Activation (ACTV)

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    • 2.4.4 READ Command

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    • 2.4.5 Write (WRT) Command

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    • 2.4.6 Mode Register Set (MRS and EMRS)

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  • 2.5 Memory Width and Byte Alignment

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  • 2.6 Endianness Support

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  • 2.7 Address Mapping

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  • 2.8 DDR2 Memory Controller Interface

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    • 2.8.1 Command Ordering and Scheduling, Advanced Concept

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    • 2.8.2 Command Starvation

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    • 2.8.3 Possible Race Condition

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  • 2.9 Refresh Scheduling

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  • 2.10 Self-Refresh Mode

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  • 2.11 Reset Considerations

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  • 2.12 VTP IO Buffer Calibration

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  • 2.13 Auto-Initialization Sequence

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    • 2.13.1 Initializing Configuration Registers

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    • 2.13.2 Initializing Following Device Power Up and Device RESET

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  • 2.14 Interrupt Support

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  • 2.15 DMA Event Support

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  • 2.16 Power Management

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    • 2.16.1 DDR2 Memory Controller Clock Stop Procedure

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  • 2.17 Emulation Considerations

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• 3 Supported Use Cases

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  • 3.1 Connecting the DDR2 Memory Controller to DDR2 Memory

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  • 3.2 Configuring Memory-Mapped Registers to Meet DDR2-400 Specification

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    • 3.2.1 Configuring SDRAM Bank Configuration Register (SDBCR)

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    • 3.2.2 Configuring SDRAM Refresh Control Register (SDRCR)

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    • 3.2.3 Configuring SDRAM Timing Registers (SDTIMR and SDTIMR2)

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    • 3.2.4 Configuring DDR PHY Control Register (DDRPHYCR)

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• 4 DDR2 Memory Controller Registers

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  • 4.1 SDRAM Status Register (SDRSTAT)

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  • 4.2 SDRAM Bank Configuration Register (SDBCR)

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  • 4.3 SDRAM Refresh Control Register (SDRCR)

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  • 4.4 SDRAM Timing Register (SDTIMR)

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  • 4.5 SDRAM Timing Register 2 (SDTIMR2)

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  • 4.6 Peripheral Bus Burst Priority Register (PBBPR)

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  • 4.7 Interrupt Raw Register (IRR)

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  • 4.8 Interrupt Masked Register (IMR)

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  • 4.9 Interrupt Mask Set Register (IMSR)

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  • 4.10 Interrupt Mask Clear Register (IMCR)

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  • 4.11 DDR PHY Control Register (DDRPHYCR)

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  • 4.12 VTP IO Control Register (VTPIOCR)

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  • 4.13 DDR VTP Register (DDRVTPR)

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  • 4.14 DDR VTP Enable Register (DDRVTPER)

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• Appendix A Revision History

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