User ManualTable of ContentsVXI-MXI User Manual1Important Information3Warranty3Copyright3Trademarks3Warning3FCC/DOC Radio Frequency Interference Compliance4Table of Contents5About This Manual10Organization of This Manual10How to Use This Manual11Related Documentation11Customer Communication11Chapter 1 General Information12Overview15Front Panel Features16What Your Kit Should Contain17Optional Equipment17Unpacking18Chapter 2 General Description19Electrical Characteristics19VMEbus Modules20VXI-MXI Functional Description23Chapter 3 Configuration and Installation28Configuring the VXI-MXI28The Metal Enclosure31VXIbus Slot 031VXIbus Logical Address33VMEbus Request Level34VMEbus Timeout Value35VMEbus Timeout Chain Position37Interlocked Arbitration Mode40MXIbus System Controller41MXIbus System Controller Timeout43MXIbus Fairness Option44CLK10 Source45EXT CLK SMB Input/Output47INTX CLK10 Mapping47Trigger Input Termination49Reset Signal Select50Installing the VXI-MXI Hardware50MXIbus Termination51INTX Termination52Installation Instructions53Connecting the INTX Cable54Connecting the MXIbus Cable55System Power Cycling Requirements57VMEbus Devices in VXIbus/MXIbus Systems58Chapter 4 Register Descriptions59Register Maps59Register Sizes59Register Description Format59Hard and Soft Reset59VXIbus Configuration Registers62VXIbus ID Register62Device Type Register64VXIbus Status/Control Register65VXIbus Extender Registers67MODID Register67Logical Address Window Register68A16 Window Map Register72A24 Window Map Register76A32 Window Map Register80INTX Interrupt Configuration Register (on VXI-MXIs with INTX only)84INTX Trigger Configuration Register (on VXI-MXIs with INTX only)85INTX Utility Configuration Register (on VXI-MXIs with INTX only)86Subclass Register88MXIbus Defined Registers89MXIbus Status/Control Register89MXIbus Lock Register94MXIbus IRQ Configuration Register95Drive Triggers/Read LA Register97Trigger Mode Selection Register99Interrupt Status/Control Register103Status/ID Register106MXIbus Trigger Configuration Register107Trigger Synchronous Acknowledge Register108IRQ Acknowledge Registers109Chapter 5 Programming Considerations110System Configuration110Planning a VXIbus/MXIbus System Logical Address Map110Base/Size Configuration Format112High/Low Configuration Format114Steps to Follow When Planning a System Logical Address Map114Worksheets for Planning Your VXIbus/MXIbus Logical Address Map122Alternative Worksheets for Planning Your VXIbus/MXIbus Logical Address Map127Planning a VXIbus/MXIbus System A16 Address Map129Worksheets for Planning Your VXIbus/MXIbus A16 Address Map137Multiframe RM Operation143Configuring the Logical Address Window143Configuring the Logical Address Window Example144Configuring the A24 and A32 Addressing Windows146System Administration and Initiation147Chapter 6 Theory of Operation148VMEbus Address and Address Modifier Transceivers148VXIbus System Controller Functions148VMEbus Data Transceivers148VMEbus Control Signals Transceivers149VMEbus Requester and Arbiter Circuitry149TTL and ECL Trigger Lines and CLK10 Circuitry149SYSFAIL, ACFAIL, and SYSRESET150Interrupt Circuitry150Parity Check and Generation153A32, A24, A16, and LA Windows153VXI-MXI Configuration Registers153MXIbus Master Mode State Machine153MXIbus Slave Mode State Machine157MXIbus Address/Data and Address Modifier Transceivers158MXIbus System Controller Functions159MXIbus Control Signals Transceivers159MXIbus Requester and Arbiter Circuitry159Appendix A Specifications162Capability Codes162VMEbus162VXIbus162MXIbus163Electrical163Environmental163Physical164Reliability164Requirements164Timing164Appendix B Mnemonics Key165Appendix C VXI-MXI Component Placement171Removing the Metal Enclosure from the VXI-MXI171Removing the INTX Daughter Card from the VXI-MXI173Installing the INTX Daughter Card onto the VXI-MXI174Appendix D Connector Descriptions175MXIbus Connector175INTX Connector177Appendix E Configuring a Two-Frame System179Configuring VXI-MXIs for a Two-Frame System179Configuration Requirements for Two-Frame System184BTO Unit184Logical Addresses184CLK10 Mapping184Appendix F Customer Communication185Glossary190Index201Figures8Figure 1-1. VXI-MXI Interface Module13Figure 1-2. VXI-MXI Interface Module with INTX Option14Figure 2-1. VXI-MXI Block Diagram24Figure 2-2. VXI-MXI INTX Daughter Card Option Block Diagram26Figure 3-1. VXI-MXI Parts Locator Diagram29Figure 3-2. VXI-MXI with INTX Parts Locator Diagram30Figure 3-3. VXIbus Slot 0 Selection31Figure 3-4. VXIbus Non-Slot 0 Selection32Figure 3-5. Logical Address Selection34Figure 3-6. VMEbus Requester Jumper Settings35Figure 3-7. VMEbus Timeout Value Selection36Figure 3-8. VMEbus Timeout; One VXI-MXI in Mainframe37Figure 3-9. VMEbus Timeout; Multiple VXI-MXIs in Mainframe38Figure 3-10. No VMEbus Timeout; Multiple VXI-MXIs in Mainframe39Figure 3-11. Interlocked Arbitration Mode Selection41Figure 3-12. MXIbus System Controller Selection42Figure 3-13. MXIbus System Controller Timeout Value Selection43Figure 3-14. MXIbus Fair Requester Selection44Figure 3-15. CLK10 Source Signal Options46Figure 3-16. EXT CLK SMB Input/Output Setting47Figure 3-17. INTX CLK10 Mapping Switches48Figure 3-18. Trigger Input Termination Option Settings49Figure 3-19. Reset Signal Selection Settings50Figure 3-20. MXIbus System51Figure 3-21. MXIbus Terminating Networks52Figure 3-22. INTX Terminator Example53Figure 3-23. MXIbus Single-Ended Cable Configuration55Figure 3-24. MXIbus Dual-Ended Cable Configuration56Figure 4-1. VXI-MXI Register Map61Figure 5-1. VXIbus/MXIbus System with Multiframe RM on a PC111Figure 5-2. VXIbus/MXIbus System with Multiframe RM in a VXIbus Mainframe111Figure 5-3. Base and Size Combinations113Figure 5-4. Address Range Allocation for Different Size Values113Figure 5-5. Example VXIbus/MXIbus System117Figure 5-6. Logical Address Map Diagram for Example VXIbus/MXIbus System118Figure 5-7. Worksheet 1 for Example VXIbus/MXIbus System119Figure 5-8. Worksheet 2 for Example VXIbus/MXIbus System120Figure 5-9. Worksheet 3 for Example VXIbus/MXIbus System121Figure 5-10. Worksheet 4 for Example VXIbus/MXIbus System121Figure 5-11. Logical Address Map Example with Alternative Worksheet128Figure 5-12. A16 Space Allocations for all Size Values130Figure 5-13. Example VXIbus/MXIbus System132Figure 5-14. Example A16 Space Address Map133Figure 5-15. Worksheet 1 for A16 Address Map Example134Figure 5-16. Worksheet 2 for A16 Map Example135Figure 5-17. Worksheet 3 for A16 Map Example136Figure 6-1. Master to Slave VMEbus/MXIbus Transfers154Figure 6-2. Deadlock Situation157Figure C-1. VXI-MXI Parts Locator Diagram172Figure C-2. VXI-MXI INTX Parts Locator Diagram (Rear View)173Figure C-3. VXI-MXI INTX Parts Locator Diagram (Front View)174Figure D-1. MXIbus Connector175Figure D-2. INTX Connector177Figure E-1. A Two-Frame VXI System179Figure E-2. VXI-MXI in Frame A without INTX180Figure E-3. VXI-MXI in Frame B without INTX181Figure E-4. VXI-MXI in Frame A with INTX182Figure E-5. VXI-MXI in Frame B with INTX183Tables9Table 2-1. VXI-MXI VMEbus Signals19Table 2-2. MXIbus Transceiver Requirements20Table 2-3. VXI-MXI VMEbus Compliance Levels21Table 3-1. MXIbus System Power Cycling Requirements57Table 4-1. VXI-MXI Register Map60Table 5-1. Base and Size Combinations112Table 5-2. Example VXIbus/MXIbus System Required Logical Addresses117Table 5-3. Amount of A16 Space Allocated for all Size Values129Table 5-4. Example VXIbus/MXIbus System Required A16 Space133Table 5-5. Logical Address Assignments for Example VXIbus/MXIbus System144Table 6-1. VXI-MXI Addresses for VMEbus Interrupt Levels152Table 6-2. VMEbus to MXIbus Address Modifier Line Map154Table 6-3. Transfer Responses for VMEbus Address Modifiers155Table 6-4. VMEbus/MXIbus Transfer Size Comparison156Table D-1. MXIbus Connector Signal Assignments175Table D-2. MXIbus Signal Groupings176Table D-3. INTX Connector Signal Assignments177Table D-4. INTX Signal Groupings178Size: 754 KBPages: 209Language: EnglishOpen manual