Manuais de utilizador para VXi 320222-01

índice analítico

• VXI-MXI User Manual

  1
• Important Information

  3
  • Warranty

    3
  • Copyright

    3
  • Trademarks

    3
  • Warning

    3
• FCC/DOC Radio Frequency Interference Compliance

  4
• Table of Contents

  5
• About This Manual

  10
  • Organization of This Manual

    10
  • How to Use This Manual

    11
  • Related Documentation

    11
  • Customer Communication

    11
• Chapter 1 General Information

  12
  • Overview

    15
  • Front Panel Features

    16
  • What Your Kit Should Contain

    17
  • Optional Equipment

    17
  • Unpacking

    18
• Chapter 2 General Description

  19
  • Electrical Characteristics

    19
  • VMEbus Modules

    20
  • VXI-MXI Functional Description

    23
• Chapter 3 Configuration and Installation

  28
  • Configuring the VXI-MXI

    28
    • The Metal Enclosure

      31
    • VXIbus Slot 0

      31
    • VXIbus Logical Address

      33
    • VMEbus Request Level

      34
    • VMEbus Timeout Value

      35
    • VMEbus Timeout Chain Position

      37
    • Interlocked Arbitration Mode

      40
    • MXIbus System Controller

      41
    • MXIbus System Controller Timeout

      43
    • MXIbus Fairness Option

      44
    • CLK10 Source

      45
    • EXT CLK SMB Input/Output

      47
    • INTX CLK10 Mapping

      47
    • Trigger Input Termination

      49
    • Reset Signal Select

      50
  • Installing the VXI-MXI Hardware

    50
    • MXIbus Termination

      51
    • INTX Termination

      52
    • Installation Instructions

      53
    • Connecting the INTX Cable

      54
    • Connecting the MXIbus Cable

      55
    • System Power Cycling Requirements

      57
  • VMEbus Devices in VXIbus/MXIbus Systems

    58
• Chapter 4 Register Descriptions

  59
  • Register Maps

    59
    • Register Sizes

      59
    • Register Description Format

      59
    • Hard and Soft Reset

      59
  • VXIbus Configuration Registers

    62
    • VXIbus ID Register

      62
    • Device Type Register

      64
    • VXIbus Status/Control Register

      65
  • VXIbus Extender Registers

    67
    • MODID Register

      67
    • Logical Address Window Register

      68
    • A16 Window Map Register

      72
    • A24 Window Map Register

      76
    • A32 Window Map Register

      80
    • INTX Interrupt Configuration Register (on VXI-MXIs with INTX only)

      84
    • INTX Trigger Configuration Register (on VXI-MXIs with INTX only)

      85
    • INTX Utility Configuration Register (on VXI-MXIs with INTX only)

      86
    • Subclass Register

      88
  • MXIbus Defined Registers

    89
    • MXIbus Status/Control Register

      89
    • MXIbus Lock Register

      94
    • MXIbus IRQ Configuration Register

      95
    • Drive Triggers/Read LA Register

      97
    • Trigger Mode Selection Register

      99
    • Interrupt Status/Control Register

      103
    • Status/ID Register

      106
    • MXIbus Trigger Configuration Register

      107
    • Trigger Synchronous Acknowledge Register

      108
    • IRQ Acknowledge Registers

      109
• Chapter 5 Programming Considerations

  110
  • System Configuration

    110
    • Planning a VXIbus/MXIbus System Logical Address Map

      110
      • Base/Size Configuration Format

        112
      • High/Low Configuration Format

        114
      • Steps to Follow When Planning a System Logical Address Map

        114
    • Worksheets for Planning Your VXIbus/MXIbus Logical Address Map

      122
    • Alternative Worksheets for Planning Your VXIbus/MXIbus Logical Address Map

      127
    • Planning a VXIbus/MXIbus System A16 Address Map

      129
    • Worksheets for Planning Your VXIbus/MXIbus A16 Address Map

      137
  • Multiframe RM Operation

    143
    • Configuring the Logical Address Window

      143
      • Configuring the Logical Address Window Example

        144
    • Configuring the A24 and A32 Addressing Windows

      146
    • System Administration and Initiation

      147
• Chapter 6 Theory of Operation

  148
  • VMEbus Address and Address Modifier Transceivers

    148
  • VXIbus System Controller Functions

    148
  • VMEbus Data Transceivers

    148
  • VMEbus Control Signals Transceivers

    149
  • VMEbus Requester and Arbiter Circuitry

    149
  • TTL and ECL Trigger Lines and CLK10 Circuitry

    149
  • SYSFAIL, ACFAIL, and SYSRESET

    150
  • Interrupt Circuitry

    150
  • Parity Check and Generation

    153
  • A32, A24, A16, and LA Windows

    153
  • VXI-MXI Configuration Registers

    153
  • MXIbus Master Mode State Machine

    153
  • MXIbus Slave Mode State Machine

    157
  • MXIbus Address/Data and Address Modifier Transceivers

    158
  • MXIbus System Controller Functions

    159
  • MXIbus Control Signals Transceivers

    159
  • MXIbus Requester and Arbiter Circuitry

    159
• Appendix A Specifications

  162
  • Capability Codes

    162
    • VMEbus

      162
    • VXIbus

      162
    • MXIbus

      163
  • Electrical

    163
  • Environmental

    163
  • Physical

    164
  • Reliability

    164
  • Requirements

    164
  • Timing

    164
• Appendix B Mnemonics Key

  165
• Appendix C VXI-MXI Component Placement

  171
  • Removing the Metal Enclosure from the VXI-MXI

    171
  • Removing the INTX Daughter Card from the VXI-MXI

    173
  • Installing the INTX Daughter Card onto the VXI-MXI

    174
• Appendix D Connector Descriptions

  175
  • MXIbus Connector

    175
  • INTX Connector

    177
• Appendix E Configuring a Two-Frame System

  179
  • Configuring VXI-MXIs for a Two-Frame System

    179
  • Configuration Requirements for Two-Frame System

    184
    • BTO Unit

      184
    • Logical Addresses

      184
    • CLK10 Mapping

      184
• Appendix F Customer Communication

  185
• Glossary

  190
• Index

  201
• Figures

  8
  • Figure 1-1. VXI-MXI Interface Module

    13
  • Figure 1-2. VXI-MXI Interface Module with INTX Option

    14
  • Figure 2-1. VXI-MXI Block Diagram

    24
  • Figure 2-2. VXI-MXI INTX Daughter Card Option Block Diagram

    26
  • Figure 3-1. VXI-MXI Parts Locator Diagram

    29
  • Figure 3-2. VXI-MXI with INTX Parts Locator Diagram

    30
  • Figure 3-3. VXIbus Slot 0 Selection

    31
  • Figure 3-4. VXIbus Non-Slot 0 Selection

    32
  • Figure 3-5. Logical Address Selection

    34
  • Figure 3-6. VMEbus Requester Jumper Settings

    35
  • Figure 3-7. VMEbus Timeout Value Selection

    36
  • Figure 3-8. VMEbus Timeout; One VXI-MXI in Mainframe

    37
  • Figure 3-9. VMEbus Timeout; Multiple VXI-MXIs in Mainframe

    38
  • Figure 3-10. No VMEbus Timeout; Multiple VXI-MXIs in Mainframe

    39
  • Figure 3-11. Interlocked Arbitration Mode Selection

    41
  • Figure 3-12. MXIbus System Controller Selection

    42
  • Figure 3-13. MXIbus System Controller Timeout Value Selection

    43
  • Figure 3-14. MXIbus Fair Requester Selection

    44
  • Figure 3-15. CLK10 Source Signal Options

    46
  • Figure 3-16. EXT CLK SMB Input/Output Setting

    47
  • Figure 3-17. INTX CLK10 Mapping Switches

    48
  • Figure 3-18. Trigger Input Termination Option Settings

    49
  • Figure 3-19. Reset Signal Selection Settings

    50
  • Figure 3-20. MXIbus System

    51
  • Figure 3-21. MXIbus Terminating Networks

    52
  • Figure 3-22. INTX Terminator Example

    53
  • Figure 3-23. MXIbus Single-Ended Cable Configuration

    55
  • Figure 3-24. MXIbus Dual-Ended Cable Configuration

    56
  • Figure 4-1. VXI-MXI Register Map

    61
  • Figure 5-1. VXIbus/MXIbus System with Multiframe RM on a PC

    111
  • Figure 5-2. VXIbus/MXIbus System with Multiframe RM in a VXIbus Mainframe

    111
  • Figure 5-3. Base and Size Combinations

    113
  • Figure 5-4. Address Range Allocation for Different Size Values

    113
  • Figure 5-5. Example VXIbus/MXIbus System

    117
  • Figure 5-6. Logical Address Map Diagram for Example VXIbus/MXIbus System

    118
  • Figure 5-7. Worksheet 1 for Example VXIbus/MXIbus System

    119
  • Figure 5-8. Worksheet 2 for Example VXIbus/MXIbus System

    120
  • Figure 5-9. Worksheet 3 for Example VXIbus/MXIbus System

    121
  • Figure 5-10. Worksheet 4 for Example VXIbus/MXIbus System

    121
  • Figure 5-11. Logical Address Map Example with Alternative Worksheet

    128
  • Figure 5-12. A16 Space Allocations for all Size Values

    130
  • Figure 5-13. Example VXIbus/MXIbus System

    132
  • Figure 5-14. Example A16 Space Address Map

    133
  • Figure 5-15. Worksheet 1 for A16 Address Map Example

    134
  • Figure 5-16. Worksheet 2 for A16 Map Example

    135
  • Figure 5-17. Worksheet 3 for A16 Map Example

    136
  • Figure 6-1. Master to Slave VMEbus/MXIbus Transfers

    154
  • Figure 6-2. Deadlock Situation

    157
  • Figure C-1. VXI-MXI Parts Locator Diagram

    172
  • Figure C-2. VXI-MXI INTX Parts Locator Diagram (Rear View)

    173
  • Figure C-3. VXI-MXI INTX Parts Locator Diagram (Front View)

    174
  • Figure D-1. MXIbus Connector

    175
  • Figure D-2. INTX Connector

    177
  • Figure E-1. A Two-Frame VXI System

    179
  • Figure E-2. VXI-MXI in Frame A without INTX

    180
  • Figure E-3. VXI-MXI in Frame B without INTX

    181
  • Figure E-4. VXI-MXI in Frame A with INTX

    182
  • Figure E-5. VXI-MXI in Frame B with INTX

    183
• Tables

  9
  • Table 2-1. VXI-MXI VMEbus Signals

    19
  • Table 2-2. MXIbus Transceiver Requirements

    20
  • Table 2-3. VXI-MXI VMEbus Compliance Levels

    21
  • Table 3-1. MXIbus System Power Cycling Requirements

    57
  • Table 4-1. VXI-MXI Register Map

    60
  • Table 5-1. Base and Size Combinations

    112
  • Table 5-2. Example VXIbus/MXIbus System Required Logical Addresses

    117
  • Table 5-3. Amount of A16 Space Allocated for all Size Values

    129
  • Table 5-4. Example VXIbus/MXIbus System Required A16 Space

    133
  • Table 5-5. Logical Address Assignments for Example VXIbus/MXIbus System

    144
  • Table 6-1. VXI-MXI Addresses for VMEbus Interrupt Levels

    152
  • Table 6-2. VMEbus to MXIbus Address Modifier Line Map

    154
  • Table 6-3. Transfer Responses for VMEbus Address Modifiers

    155
  • Table 6-4. VMEbus/MXIbus Transfer Size Comparison

    156
  • Table D-1. MXIbus Connector Signal Assignments

    175
  • Table D-2. MXIbus Signal Groupings

    176
  • Table D-3. INTX Connector Signal Assignments

    177
  • Table D-4. INTX Signal Groupings

    178