Cypress CY7C68033 Manual De Usuario
CY7C68033/CY7C68034
Document #: 001-04247 Rev. *D
Page 10 of 33
Default High-Speed Alternate Settings
External FIFO Interface
Architecture
The NX2LP-Flex slave FIFO architecture has eight 512-byte
blocks in the endpoint RAM that directly serve as FIFO
memories, and are controlled by FIFO control signals (such as
SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags).
blocks in the endpoint RAM that directly serve as FIFO
memories, and are controlled by FIFO control signals (such as
SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags).
In operation, some of the eight RAM blocks fill or empty from
the SIE, while the others are connected to the I/O transfer
logic. The transfer logic takes two forms, the GPIF for internally
generated control signals, or the slave FIFO interface for
externally controlled transfers.
the SIE, while the others are connected to the I/O transfer
logic. The transfer logic takes two forms, the GPIF for internally
generated control signals, or the slave FIFO interface for
externally controlled transfers.
Master/Slave Control Signals
The NX2LP-Flex endpoint FIFOS are implemented as eight
physically distinct 256x16 RAM blocks. The 8051/SIE can
switch any of the RAM blocks between two domains, the USB
(SIE) domain and the 8051-I/O Unit domain. This switching is
done virtually instantaneously, giving essentially zero transfer
time between ‘USB FIFOS’ and ‘Slave FIFOS.’ Since they are
physically the same memory, no bytes are actually transferred
between buffers.
physically distinct 256x16 RAM blocks. The 8051/SIE can
switch any of the RAM blocks between two domains, the USB
(SIE) domain and the 8051-I/O Unit domain. This switching is
done virtually instantaneously, giving essentially zero transfer
time between ‘USB FIFOS’ and ‘Slave FIFOS.’ Since they are
physically the same memory, no bytes are actually transferred
between buffers.
At any given time, some RAM blocks are filling/emptying with
USB data under SIE control, while other RAM blocks are
available to the 8051 and/or the I/O control unit. The RAM
blocks operate as single-port in the USB domain, and
dual-port in the 8051-I/O domain. The blocks can be
configured as single, double, triple, or quad buffered as previ-
ously shown.
USB data under SIE control, while other RAM blocks are
available to the 8051 and/or the I/O control unit. The RAM
blocks operate as single-port in the USB domain, and
dual-port in the 8051-I/O domain. The blocks can be
configured as single, double, triple, or quad buffered as previ-
ously shown.
The I/O control unit implements either an internal-master (M
for master) or external-master (S for Slave) interface.
for master) or external-master (S for Slave) interface.
In Master (M) mode, the GPIF internally controls
FIFOADR[1:0] to select a FIFO. The two RDY pins can be
used as flag inputs from an external FIFO or other logic if
desired. The GPIF can be run from an internally derived clock
FIFOADR[1:0] to select a FIFO. The two RDY pins can be
used as flag inputs from an external FIFO or other logic if
desired. The GPIF can be run from an internally derived clock
(IFCLK), at a rate that transfers data up to 96 Megabytes/s
(48-MHz IFCLK with 16-bit interface).
(48-MHz IFCLK with 16-bit interface).
In Slave (S) mode, the NX2LP-Flex accepts an internally
derived clock (IFCLK, max. frequency 48 MHz) and SLCS#,
SLRD, SLWR, SLOE, PKTEND signals from external logic.
Each endpoint can individually be selected for byte or word
operation by an internal configuration bit, and a Slave FIFO
Output Enable signal SLOE enables data of the selected
width. External logic must ensure that the output enable signal
is inactive when writing data to a slave FIFO. The slave
interface must operate asynchronously, where the SLRD and
SLWR signals act directly as strobes, rather than a clock
qualifier as in a synchronous mode. The signals SLRD, SLWR,
SLOE and PKTEND are gated by the signal SLCS#.
derived clock (IFCLK, max. frequency 48 MHz) and SLCS#,
SLRD, SLWR, SLOE, PKTEND signals from external logic.
Each endpoint can individually be selected for byte or word
operation by an internal configuration bit, and a Slave FIFO
Output Enable signal SLOE enables data of the selected
width. External logic must ensure that the output enable signal
is inactive when writing data to a slave FIFO. The slave
interface must operate asynchronously, where the SLRD and
SLWR signals act directly as strobes, rather than a clock
qualifier as in a synchronous mode. The signals SLRD, SLWR,
SLOE and PKTEND are gated by the signal SLCS#.
GPIF and FIFO Clock Rates
An 8051 register bit selects one of two frequencies for the
internally supplied interface clock: 30 MHz and 48 MHz. A bit
within the IFCONFIG register will invert the IFCLK signal.
internally supplied interface clock: 30 MHz and 48 MHz. A bit
within the IFCONFIG register will invert the IFCLK signal.
The default NAND firmware image implements a 48-MHz
internally supplied interface clock. The NAND boot logic uses
the same configuration to implement 100-ns timing on the
NAND bus to support proper detection of all NAND Flash
types.
internally supplied interface clock. The NAND boot logic uses
the same configuration to implement 100-ns timing on the
NAND bus to support proper detection of all NAND Flash
types.
GPIF
The GPIF is a flexible 8- or 16-bit parallel interface driven by a
user-programmable finite state machine. It allows the
NX2LP-Flex to perform local bus mastering, and can
implement a wide variety of protocols such as 8-bit NAND
interface, printer parallel port, and Utopia. The default NAND
firmware and boot logic utilizes GPIF functionality to interface
with NAND Flash.
user-programmable finite state machine. It allows the
NX2LP-Flex to perform local bus mastering, and can
implement a wide variety of protocols such as 8-bit NAND
interface, printer parallel port, and Utopia. The default NAND
firmware and boot logic utilizes GPIF functionality to interface
with NAND Flash.
The GPIF on the NX2LP-Flex features three programmable
control outputs (CTL) and two general-purpose ready inputs
(RDY). The GPIF data bus width can be 8 or 16 bits. Because
control outputs (CTL) and two general-purpose ready inputs
(RDY). The GPIF data bus width can be 8 or 16 bits. Because
ep4
0
64 bulk out (2×)
64 bulk out (2×)
64 bulk out (2×)
ep6
0
64 bulk in (2×)
64 int in (2×)
64 iso in (2×)
ep8
0
64 bulk in (2×)
64 bulk in (2×)
64 bulk in (2×)
Table 6. Default Full-Speed Alternate Settings
[2, 3]
(continued)
Note
4. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.
Table 7. Default High-Speed Alternate Settings
Alternate Setting
0
1
2
3
ep0
64
64
64
64
ep1out
0
512 bulk
64 int
64 int
ep1in
0
512 bulk
64 int
64 int
ep2
0
512 bulk out (2×)
512 int out (2×)
512 iso out (2×)
ep4
0
512 bulk out (2×)
512 bulk out (2×)
512 bulk out (2×)
ep6
0
512 bulk in (2×)
512 int in (2×)
512 iso in (2×)
ep8
0
512 bulk in (2×)
512 bulk in (2×)
512 bulk in (2×)