Cypress CY8C24423 Manual De Usuario
CY8C24123
CY8C24223, CY8C24423
Document Number: 38-12011 Rev. *G
Page 23 of 43
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C
and -40°C
≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling
of the digital signal may appear on the AGND.
of the digital signal may appear on the AGND.
Table 20. 5V DC Analog Reference Specifications
Symbol
Description
Min
Typ
Max
Units
BG
Bandgap Voltage Reference
1.274
1.30
1.326
V
–
AGND = Vdd/2
a
CT Block Power = High
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 2%.
Vdd/2 - 0.043
Vdd/2 - 0.025
Vdd/2 + 0.003
V
–
AGND = 2 x BandGap
a
CT Block Power = High
2 x BG - 0.048
2 x BG - 0.030
2 x BG + 0.024
V
–
AGND = P2[4] (P2[4] = Vdd/2)
a
CT Block Power = High
P2[4] - 0.013
P2[4]
P2[4] + 0.014
V
–
AGND = BandGap
a
CT Block Power = High
BG - 0.009
BG + 0.008
BG + 0.016
V
–
AGND = 1.6 x BandGap
a
CT Block Power = High
1.6 x BG - 0.022
1.6 x BG - 0.010
1.6 x BG + 0.018
V
–
AGND Column to Column Variation (AGND =
Vdd/2)
Vdd/2)
a
CT Block Power = High
-0.034
0.000
0.034
V
–
RefHi = Vdd/2 + BandGap
Ref Control Power = High
Ref Control Power = High
Vdd
/2 + BG - 0.140
Vdd
/2 + BG - 0.018
Vdd
/2 + BG +
0.103
V
–
RefHi = 3 x BandGap
Ref Control Power = High
Ref Control Power = High
3 x BG - 0.112
3 x BG - 0.018
3 x BG + 0.076
V
–
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
Ref Control Power = High
Ref Control Power = High
2 x BG + P2[6] -
0.113
2 x BG + P2[6] -
0.018
2 x BG + P2[6] +
0.077
V
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
Ref Control Power = High
Ref Control Power = High
P2[4] + BG - 0.130 P2[4] + BG - 0.016 P2[4] + BG + 0.098
V
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
Ref Control Power = High
Ref Control Power = High
P2[4] + P2[6] - 0.133
P2[4] + P2[6] -
0.016
P2[4] + P2[6]+
0.100
V
–
RefHi = 3.2 x BandGap
Ref Control Power = High
Ref Control Power = High
3.2 x BG - 0.112
3.2 x BG
3.2 x BG + 0.076
V
–
RefLo = Vdd/2 – BandGap
Ref Control Power = High
Ref Control Power = High
Vdd
/2 - BG - 0.051
Vdd
/2 - BG
+
0.024
Vdd
/2 - BG + 0.098
V
–
RefLo = BandGap
Ref Control Power = High
Ref Control Power = High
BG - 0.082
BG + 0.023
BG + 0.129
V
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
Ref Control Power = High
Ref Control Power = High
2 x BG - P2[6] -
0.084
2 x BG - P2[6] +
0.025
2 x BG - P2[6] +
0.134
V
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
Ref Control Power = High
Ref Control Power = High
P2[4] - BG - 0.056
P2[4] - BG + 0.026 P2[4] - BG + 0.107
V
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
Ref Control Power = High
Ref Control Power = High
P2[4] - P2[6] - 0.057
P2[4] - P2[6] +
0.026
P2[4] - P2[6] +
0.110
V