Cypress CY8C20396 Manual De Usuario
CY8C20x36/46/66, CY8C20396
Document Number: 001-12696 Rev. *D
Page 14 of 34
48-Pin QFN OCD
The 48-pin QFN part is for the CY8C20066 On-Chip Debug (OCD) PSoC device. Note that this part is only used for in-circuit
debugging.
debugging.
[4]
Table 8. Pin Definitions - CY8C20066 PSoC Device
Pin
No.
No.
Di
gi
ta
l
Analog
Name
Description
Figure 8. CY8C20066 PSoC Device
1
OCDOE
OCD mode direction pin
2
IO
I
P2[7]
3
IO
I
P2[5]
Crystal output (XOut)
4
IO
I
P2[3]
Crystal input (XIn)
5
IO
I
P2[1]
6
IO
I
P4[3]
7
IO
I
P4[1]
8
IO
I
P3[7]
9
IO
I
P3[5]
10
IO
I
P3[3]
11
IO
I
P3[1]
12
IOHR
I
P1[7]
I2C SCL, SPI SS
13
IOHR
I
P1[5]
I2C SDA, SPI MISO
14
CCLK
OCD CPU clock output
15
HCLK
OCD high speed clock output
16
IOHR
I
P1[3]
SPI CLK.
17
IOHR
I
P1[1]
ISSP CLK
, I2C SCL, SPI MOSI
18
Power
Vss
Ground connection
19
IO
D+
20
IO
D-
21
Power
Vdd
Supply voltage
22
IOHR
I
P1[0]
ISSP DATA
(1)
, I2C SDA, SPI CLK
23
IOHR
I
P1[2]
Pin
No.
No.
Di
gi
ta
l
An
a
log
Name
Description
24
IOHR
I
P1[4]
Optional external clock input
(EXTCLK)
(EXTCLK)
37
IOH
I
P0[0]
25
IOHR
I
P1[6]
38
IOH
I
P0[2]
26
Input
XRES
Active high external reset with
internal pull down
internal pull down
39
IOH
I
P0[4]
27
IO
I
P3[0]
40
IOH
I
P0[6]
28
IO
I
P3[2]
41
Power
Vdd
Supply voltage
29
IO
I
P3[4]
42
OCDO
OCD even data IO
30
IO
I
P3[6]
43
OCDE
OCD odd data output
31
IO
I
P4[0]
44
IOH
I
P0[7]
32
IO
I
P4[2]
45
IOH
I
P0[5]
33
IO
I
P2[0]
46
IOH
I
P0[3]
Integrating input
34
IO
I
P2[2]
47
Power
Vss
Ground connection
35
IO
I
P2[4]
48
IOH
I
P0[1]
36
IO
I
P2[6]
CP
Power
Vss
Center pad must be connected to ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
QFN
(Top View)
Vs
s
P0[3
], AI
P0
[5
], AI
P0[7
], AI
Vd
d
P0
[6
],
A
I
P0[2
], AI
P0[0
], AI
10
11
12
11
12
A
I
, P2[7]
AI, XOut, P2[5]
AI, XIn , P2[3]
AI , P2[1]
AI , P4[3]
AI , P4[1]
AI, P3[7]
AI, P3[5]
AI, P3[3]
AI, P3[1]
AI, P3[3]
AI, P3[1]
AI, I2C SCL, SPI SS, P1[7]
35
34
33
32
31
30
29
28
27
26
25
34
33
32
31
30
29
28
27
26
25
36
48
47
46
45
44
43
42
41
40
39
38
37
P2[4], AI
P2[2], AI
P2[0], AI
P2[0], AI
P4[2], AI
P4[0], AI
P4[0], AI
P3[6], AI
P3[4 ], AI
P3[2], AI
P3[0 ], AI
P3[4 ], AI
P3[2], AI
P3[0 ], AI
XRES
P1[6], AI
P2[6], AI
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
20
21
22
23
24
I2C
S
D
A,
S
PI
MI
SO
, A
I,
P1[
5]
SP
I C
LK
, A
I,
P1[
3]
AI, C
LK
6
, I2
C SC
L,
SPI M
O
SI
, P1
[1
]
Vs
s
D+
D-
Vdd
AI
, DATA
1
, I2
C
SDA,
SP
I CLK, P1[0]
AI
, P
1[
2]
AI,
EXTC
LK,
P
1[
4]
P0[4
], AI
P0
[1
], AI
OCDO
E
CC
LK
HC
LK
OC
DE
OC
DO
Note
4. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes.