Cypress CY8C20396 Manual De Usuario
CY8C20x36/46/66, CY8C20396
Document Number: 001-12696 Rev. *D
Page 28 of 34
Figure 18. 48-Pin (7x7 mm) QFN
Important Notes
■
For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
■
Pinned vias for thermal conduction are not required for the low power PSoC device.
Thermal Impedances
Solder Reflow Peak Temperature
This table lists the minimum solder reflow peak temperature to achieve good solderability.
001-13191 *C
Table 33. Thermal Impedances per Package
Package
Typical
θ
JA
16 QFN
32.69
o
C/W
24 QFN
20.90
o
C/W
32 QFN
19.51
o
C/W
48 SSOP
69
o
C/W
48 QFN
17.68
o
C/W
Table 34. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature
Maximum Peak Temperature
16 QFN
240
o
C
260
o
C
24 QFN
240
o
C
260
o
C
32 QFN
240
o
C
260
o
C
48 SSOP
220
o
C
260
o
C
48 QFN
240
o
C
260
o
C
Notes
11. T
J
= T
A
+ Power x
θ
JA
.
12. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane.
13. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5
13. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5
o
C with Sn-Pb or 245 ± 5
o
C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.