Cypress CY7C64113C Manual De Usuario
CY7C64013C
CY7C64113C
Document #: 38-08001 Rev. *B
Page 35 of 51
Bits[6..0] :Device Address
Firmware writes this bits during the USB enumeration process to the non-zero address assigned by the USB host.
Bit 7
:Device Address Enable
Must be set by firmware before the SIE can respond to USB traffic to the Device Address.
Bit 7 (Device Address Enable) in the USB Device Address Register must be set by firmware before the SIE can respond to USB
traffic to this address. The Device Addresses in bits [6:0] are set by firmware during the USB enumeration process to the non-
zero address assigned by the USB host.
traffic to this address. The Device Addresses in bits [6:0] are set by firmware during the USB enumeration process to the non-
zero address assigned by the USB host.
18.2
USB Device Endpoints
The CY7C64x13C controller supports one USB device address and five endpoints for communication with the host. The config-
uration of these endpoints, and associated FIFOs, is controlled by bits [7,6] of the USB Status and Control Register (0x1F). Bit 7
controls the size of the endpoints and bit 6 controls the number of endpoints. These configuration options are detailed in Table
18-1. The “unused” FIFO areas in the following table can be used by the firmware as additional user RAM space.
When the SIE writes data to a FIFO, the internal data bus is driven by the SIE; not the CPU. This causes a short delay in the
CPU operation. The delay is three clock cycles per byte. For example, an 8-byte data write by the SIE to the FIFO generates a
delay of 2 µs (3 cycles/byte * 83.33 ns/cycle * 8 bytes).
18.3
USB Control Endpoint Mode Register
All USB devices are required to have a Control Endpoint 0 (EPA0) that is used to initialize and control each USB address. Endpoint
0 provides access to the device configuration information and allows generic USB status and control accesses. Endpoint 0 is
bidirectional to both receive and transmit data. The other endpoints are unidirectional, but selectable by the user as IN or OUT
endpoints.
The endpoint mode register is cleared during reset. The endpoint zero EPA0 mode register uses the format shown in Figure 18-2.
The endpoint mode register is cleared during reset. The endpoint zero EPA0 mode register uses the format shown in Figure 18-2.
USB Device Endpoint Zero Mode
ADDRESSES
0x12)
Bits[3..0] : Mode
These sets the mode which control how the control endpoint responds to traffic.
Bit 4 : ACK
This bit is set whenever the SIE engages in a transaction to the register’s endpoint that completes with an ACK packet.
Bit 5: Endpoint 0 OUT Received
1= Token received is an OUT token. 0= Token received is not an OUT token. This bit is set by the SIE to report the type of
token received by the corresponding device address is an OUT token. The bit must be cleared by firmware as part of the
USB processing.
Table 18-1. Memory Allocation for Endpoints
USB Status And Control Register (0x1F) Bits [7, 6]
[0,0]
[1,0]
[0,1]
[1,1]
Label
Start
Address
Size
Label
Start
Address
Size
Label
Start
Address
Size
Label
Start
Address
Size
unused
0xD8
8
unused
0xA8
8
EPA4
0xD8
8
EPA4
0xB0
8
unused
0xE0
8
unused
0xB0
8
EPA3
0xE0
8
EPA3
0xA8
8
EPA2
0xE8
8
EPA0
0xB8
8
EPA2
0xE8
8
EPA0
0xB8
8
EPA1
0xF0
8
EPA1
0xC0
32
EPA1
0xF0
8
EPA1
0xC0
32
EPA0
0xF8
8
EPA2
0xE0
32
EPA0
0xF8
8
EPA2
0xE0
32
Bit #
7
6
5
4
3
2
1
0
Bit Name
Endpoint 0 SETUP
Received
Endpoint 0 IN
Received
Endpoint 0 OUT
Received
ACK
Mode Bit 3
Mode Bit 2
Mode Bit 1
Mode Bit 0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Figure 18-2. USB Device Endpoint Zero Mode Registers