Cypress CY7C64113C Manual De Usuario

Document #: 38-08001 Rev. *B

Page 37 of 51

Bits[5..0] : Byte Count

These counter bits indicate the number of data bytes in a transaction. For IN transactions, firmware loads the count with

the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 32, inclusive. For OUT or

SETUP transactions, the count is updated by hardware to the number of data bytes received, plus 2 for the CRC bytes.

Valid values are 2 to 34, inclusive.

Bit 6 : Data Valid

This bit is set on receiving a proper CRC when the endpoint FIFO buffer is loaded with data during transactions. This bit is

used OUT and SETUP tokens only. If the CRC is not correct, the endpoint interrupt occurs, but Data Valid is cleared to a

zero. 

Bit 7 : Data 0/1 Toggle 

This bit selects the DATA packet’s toggle state: 0 for DATA0, 1 for DATA1. For IN transactions, firmware must set this bit to

the desired state. For OUT or SETUP transactions, the hardware sets this bit to the state of the received Data Toggle bit.

Whenever the count updates from a SETUP or OUT transaction on endpoint 0, the counter register locks and cannot be written

by the CPU. Reading the register unlocks it. This prevents firmware from overwriting a status update on incoming SETUP or OUT

transactions before firmware has a chance to read the data. Only endpoint 0 counter register is locked when updated. The locking

mechanism does not apply to the count registers of other endpoints.

The contents of the endpoint mode and counter registers are updated, based on the packet flow diagram in Figure 18-5. Two

time points, UPDATE and SETUP, are shown in the same figure. The following activities occur at each time point:
SETUP:
The SETUP bit of the endpoint 0 mode register is forced HIGH at this time. This bit is forced HIGH by the SIE until the end of the

data phase of a control write transfer. The SETUP bit can not be cleared by firmware during this time.
The affected mode and counter registers of endpoint 0 are locked from any CPU writes once they are updated. These registers

can be unlocked by a CPU read, only if the read operation occurs after the UPDATE. The firmware needs to perform a register

read as a part of the endpoint ISR processing to unlock the effected registers. The locking mechanism on mode and counter

registers ensures that the firmware recognizes the changes that the SIE might have made since the previous IO read of that

register.
UPDATE:

1. Endpoint Mode Register – All the bits are updated (except the SETUP bit of the endpoint 0 mode register).
2. Counter Registers – All bits are updated.
3. Interrupt – If an interrupt is to be generated as a result of the transaction, the interrupt flag for the corresponding endpoint is 

set at this time. For details on what conditions are required to generate an endpoint interrupt, refer to Table 19-2.

4. The contents of the updated endpoint 0 mode and counter registers are locked, except the SETUP bit of the endpoint 0 mode 

register which was locked earlier.