Cypress STK14C88-3 Manual De Usuario
STK14C88-3
256 Kbit (32K x 8) AutoStore nvSRAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-50592 Rev. **
Revised January 29, 2009
Features
■
35 ns and 45 ns access times
■
Automatic nonvolatile STORE on power loss
■
Nonvolatile STORE under Hardware or Software control
■
Automatic RECALL to SRAM on power up
■
Unlimited Read/Write endurance
■
Unlimited RECALL cycles
■
1,000,000 STORE cycles
■
100 year data retention
■
Single 3.3V+0.3V power supply
■
Commercial and Industrial Temperatures
■
32-pin (300mil) SOIC and 32-pin (600 mil) PDIP packages
■
RoHS compliance
Functional Description
The Cypress STK14C88-3 is a 256 Kb fast static RAM with
a nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap
a nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap
™
technology producing the world’s most reliable nonvolatile
memory. The SRAM provides unlimited read and write
cycles, while independent, nonvolatile data resides in the
highly reliable QuantumTrap cell. Data transfers from the
SRAM to the nonvolatile elements (the STORE operation)
takes place automatically at power down. On power up, data
is restored to the SRAM (the RECALL operation) from the
nonvolatile memory. Both the STORE and RECALL opera-
tions are also available under software control.
memory. The SRAM provides unlimited read and write
cycles, while independent, nonvolatile data resides in the
highly reliable QuantumTrap cell. Data transfers from the
SRAM to the nonvolatile elements (the STORE operation)
takes place automatically at power down. On power up, data
is restored to the SRAM (the RECALL operation) from the
nonvolatile memory. Both the STORE and RECALL opera-
tions are also available under software control.
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
512 X 512
Quantum Trap
512 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
ROW DECODER
INPUT
BUFFERS
OE
CE
WE
WE
HSB
V
CC
V
CAP
A
13
-
A
0
A
0
A
1
A
2
A
3
A
4
A
10
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Logic Block Diagram