Cypress STK14C88-3 Manual De Usuario
STK14C88-3
Document Number: 001-50592 Rev. **
Page 3 of 17
Device Operation
The STK14C88-3 nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The STK14C88-3 supports unlimited reads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL opera-
tions from the nonvolatile cells and up to one million STORE
operations.
nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The STK14C88-3 supports unlimited reads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL opera-
tions from the nonvolatile cells and up to one million STORE
operations.
SRAM Read
The STK14C88-3 performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
are LOW while WE and HSB are HIGH. The address specified
on pins A
0–14
determines the 32,768 data bytes accessed. When
the READ is initiated by an address transition, the outputs are
valid after a delay of t
valid after a delay of t
AA
(READ cycle 1). If the READ is initiated
by CE or OE, the outputs are valid at t
ACE
or at t
DOE
, whichever
is later (READ cycle 2). The data outputs repeatedly respond to
address changes within the t
address changes within the t
AA
access time without the need for
transitions on any control input pins, and remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the WRITE cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle. The data on the common IO
pins DQ
HSB is HIGH. The address inputs must be stable prior to entering
the WRITE cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle. The data on the common IO
pins DQ
0–7
are written into the memory if it has valid t
SD
, before
the end of a WE controlled WRITE or before the end of an CE
controlled WRITE. Keep OE HIGH during the entire WRITE cycle
to avoid data bus contention on common IO lines. If OE is left
LOW, internal circuitry turns off the output buffers t
controlled WRITE. Keep OE HIGH during the entire WRITE cycle
to avoid data bus contention on common IO lines. If OE is left
LOW, internal circuitry turns off the output buffers t
HZWE
after WE
goes LOW.
AutoStore
®
Operation
The STK14C88-3 can be powered in one of three storage opera-
tions:
tions:
During normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
shows the proper connection of the storage capacitor
(V
CAP
) for automatic store operation. A charge storage capacitor
having a capacity of between 68 uF and 220 uF (+20%) rated at
4.7V should be provided.
4.7V should be provided.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull-up resistor is shown connected to HSB
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull-up resistor is shown connected to HSB
.
The HSB signal is monitored by the system to detect if an
AutoStore cycle is in progress.
AutoStore cycle is in progress.
If the power supply drops faster than 20 us/volt before Vcc
reaches V
reaches V
SWITCH
, then a 1 ohm resistor should be connected
between V
CC
and the system supply to avoid momentary excess
of current between V
CC
and V
CAP
.
AutoStore Inhibit Mode
If an automatic STORE
on power loss is not required, then V
CC
is tied to ground and +3.3V is applied to V
CAP
(
). This is
the AutoStore Inhibit mode, where the AutoStore function is
disabled. If the STK14C88-3 is operated in this configuration,
references to V
disabled. If the STK14C88-3 is operated in this configuration,
references to V
CC
are changed to V
CAP
throughout this data
sheet. In this mode, STORE
operations are triggered through
software control. It is not permissible to change between these
options “On the fly”.
options “On the fly”.
Figure 2. AutoStore Mode