Cypress CYS25G0101DX-ATC Manual De Usuario
CYS25G0101DX-ATC Evaluation Board User’s Guide
5
Figure 1. The Block Diagram of the CYS25G0101DX
TXD
15:0
15:0
TX PLL
x16
/16
RXD
15:0
(155.52MHz)
REFCLK
(155.52MHz)
RXCLKOUT
SHIFTER
RX CDR
PLL
TXCLKO
Input
Register
Output
Register
FIFO
(5byte)
SHIFTER
(155.52MHz)
TXCLKI
/16
DIAGLOOP
LINELOOP
LOOPA
LOOPA
IN
±
OUT
±
Lock-to-Data /
Clock Control
Logic
LOOPTIME
FIFO_RST
FIFO_ERR
RESET
LFI
SD
LOCKREF
PWRDN
Retimed
Data
Recovered
Bit-Clock
Bit-Clock
Lock-to-Ref
Tx Bit-Clock