Manual De UsuarioTabla de contenidos1. Introduction42. Features43. Kit Contents44. Functional Description45. Diagnostic Modes125.1 Diagnostic Loopback Mode125.2 Line Loopback135.3 Analog Line Loopback145.4 “Parallel Line Loopback” (TEST0) Mode155.4.1 Test the Internal RX CDR PLL Only155.4.2 Test the Internal RX CDR PLL and TX PLL156. Testing Hookup166.1 Set-up for BERT Test166.2 Set-up for Eye Diagram Test176.3 SONET Jitter Transfer and Jitter Tolerance Test186.4 Set-up for Testing the TX PLL in Parallel Line Loopback Mode197. Eye Diagram Testing Result208. Jitter Transfer Testing Result219. Jitter Tolerance Testing Result2210. Schematic Diagram, PCB Layout and BOM (Bill of Material)23Appendix A: Schematic Diagrams of the CYS25G0101DX Evaluation Board24Appendix B: PCB Layout Diagrams of the CYS25G0101DX Evaluation Board32Appendix C: CYS25G0101DX Evaluation Board LVPECL BOM (Bill of Material)42Appendix D: CYS25G0101DX Evaluation Board HSTL BOM (Bill of Material)47Figure 1. The Block Diagram of the CYS25G0101DX5Figure 2. The CYS25G0101DX Evaluation Board6Figure 3. The Jumper Orientations of the CYS25G0101DX11Figure 4. Diagnostic Loopback Mode Data Path12Figure 5. Line Loopback Mode Data Path13Figure 6. Analog Line Loopback Mode Data Path14Figure 7. Parallel Loopback (TEST0) Mode Data Path15Figure 8. Equipment Set-up for BERT Test16Figure 9. Equipment Set-up For Eye Diagram Test17Figure 10. Equipment Set-up For Jitter Test18Figure 11. Equipment Set-up For Testing the TX PLL in Parallel Line Loopback Mode19Figure 12. CYS25G0101DX Evaluation Board Eye Diagram20Figure 13. CYS25G0101DX Evaluation Board GR-253 Jitter Transfer Testing Result21Figure 14. CYS25G0101DX Evaluation Board G958 Jitter Transfer Testing Result21Figure 15. CYS25G0101DX Evaluation Board GR-253 JitterTolerance Testing Result22Figure 16. CYS25G0101DX Evaluation Board G825 Jitter Tolerance Testing Result22Figure 17. Top Level of CYS25G0101DX Evaluation Board Schematic Diagram25Figure 18. Parallel Output Block Schematic Diagram26Figure 19. Parallel Input Block Schematic Diagram27Figure 20. Signals Block Schematic Diagram28Figure 21. Power Supply Block Schematic Diagram29Figure 22. Control Block Schematic Diagram30Figure 23. Reference Clock Block Schematic Diagram31Figure 24. CYS25G0101DX Evaluation Board PCB Mechanical Drawing33Figure 25. CYS25G0101DX Evaluation Board PCB Top Layer Silk Screen34Figure 26. CYS25G0101DX Evaluation Board PCB Top Layer Layout35Figure 27. CYS25G0101DX Evaluation Board PCB Top Layer Solder Mask36Figure 28. CYS25G0101DX Evaluation Board PCB Power Plane Layout37Figure 29. CYS25G0101DX Evaluation Board PCB Ground Plane Layout38Figure 30. CYS25G0101DX Evaluation Board PCB Bottom Silk Screen39Figure 31. CYS25G0101DX Evaluation Board PCB Bottom Layer Layout40Figure 32. CYS25G0101DX Evaluation Board PCB Bottom Solder Mask41Table 1. Functional Description of the Connectors6Table 2. Pin Assignment of J1 Header and Description of J10 Header7Table 3. Pin Assignment of J2 Header and Description of J9 Header8Table 4. Functional Description of DIP Switch 1 (SW1)9Table 5. Functional Description of J4 Connector10Table 6. Description of LED Indicators10Table 7. Operation Specification of CYS25G0101DX Evaluation Board23Table 8. CYS25G0101DX Evaluation Board LVPECL BOM - Page 1 of 443Table 9. CYS25G0101DX Evaluation Board LVPECL BOM - Page 2 of 444Table 10. CYS25G0101DX Evaluation Board LVPECL BOM - Page 3 of 445Table 11. CYS25G0101DX Evaluation Board LVPECL BOM - Page 4 of 446Table 12. CYS25G0101DX Evaluation Board HSTL BOM - Page 1 of 448Table 13. CYS25G0101DX Evaluation Board HSTL BOM - Page 2 of 449Table 14. CYS25G0101DX Evaluation Board HSTL BOM - Page 3 of 450Table 15. CYS25G0101DX Evaluation Board HSTL BOM - Page 4 of 451Tamaño: 2 MBPáginas: 51Language: EnglishManuales abiertas