Cypress CY7C64013C Manual De Usuario

Document #: 38-08001 Rev. *B

Page 24 of 51

Internal hardware supports communication with external devices through two interfaces: a two-wire I

2

C-compatible interface, and

a HAPI for 1, 2, or 3 byte transfers. The I

2

C-compatible interface and HAPI functions, discussed in detail in Sections 13.0 and

14.0, share a common configuration register (see Figure 12-1). All bits of this register are cleared on reset.
I

Note: I

Bits [7,1:0] of the HAPI/I

2

C Configuration Register control the pin out configuration of the HAPI and I

2

C-compatible interfaces.

Bits [5:2] are used in HAPI mode only, and are described in Section 14.0. Table 12-1 shows the HAPI port configurations, and

Table 12-2 shows I

2

C pin location configuration options. These I

2

C-compatible options exist due to pin limitations in certain

packages, and to allow simultaneous HAPI and I

2

C-compatible operation.

HAPI operation is enabled whenever either HAPI Port Width Bit (Bit 1 or 0) is non-zero. This affects GPIO operation as described

in Section 14.0. I

2

C-compatible blocks must be separately enabled as described in Section 13.0. 

7

6

5

4

3

2

1

0

Reserved

Reserved

Reserved

Reserved

Timer Bit 11

Timer Bit 10

Timer Bit 9

Timer Bit 8

-

-

-

-

R

R

R

R

0

0

0

0

0

0

0

0

 

7

6

5

4

3

2

1

0

I

2

C Position

Reserved

LEMPTY 

Polarity

DRDY 

Polarity

Latch 

Empty

Data 

Ready

HAPI Port Width 

Bit 1

HAPI Port Width 

Bit 0

R/W

-

R/W

R/W

R

R

R/W

R/W

0

0

0

0

0

0

0

0

10 9

7

8

5

6

4

3

2

1-MHz Clock

1.024-ms Interrupt
128-

 µ

s Interrupt

To Timer Register

8

1

0

11

L1 L0

L2

L3

D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0