Cypress CY7C64013C Manual De Usuario

Document #: 38-08001 Rev. *B

Page 25 of 51

  

The I

2

C-compatible block provides a versatile two-wire communication with external devices, supporting master, slave, and multi-

master modes of operation. The I

2

C-compatible block functions by handling the low-level signaling in hardware, and issuing

interrupts as needed to allow firmware to take appropriate action during transactions. While waiting for firmware response, the

hardware keeps the I

2

C-compatible bus idle if necessary.

The I

2

C-compatible block generates an interrupt to the microcontroller at the end of each received or transmitted byte, when a

stop bit is detected by the slave when in receive mode, or when arbitration is lost. Details of the interrupt responses are given in

Section 16.8. 
The I

2

C-compatible interface consists of two registers, an I

2

C Data Register (Figure 13-1) and an I

2

C Status and Control Register

(Figure 13-2). The Data Register is implemented as separate read and write registers. Generally, the I

2

C Status and Control

Register should only be monitored after the I

2

C interrupt, as all bits are valid at that time. Polling this register at other times could

read misleading bit status if a transaction is underway.
The I

2

C SCL clock is connected to bit 0 of GPIO port 1 or GPIO port 2, and the I

2

C SDA data is connected to bit 1 of GPIO port

1 or GPIO port 2. Refer to Section 12.0 for the bit definitions and functionality of the HAPI/I

2

C Configuration Register, which is

used to set the locations of the configurable I

2

C-compatible pins. Once the I

2

C-compatible functionality is enabled by setting bit

0 of the I

2

C Status & Control Register, the two LSB bits ([1:0]) of the corresponding GPIO port are placed in Open Drain mode,

regardless of the settings of the GPIO Configuration Register.The electrical characteristics of the I

2

C-compatible interface is the

same as that of GPIO ports 1 and 2. Note that the I

OL 

(max) is 2 mA @ V

OL 

= 2.0 V for ports 1 and 2.

All control of the I

2

C clock and data lines is performed by the I

2

C-compatible block. 

I

Contains the 8 bit data on the I

2

C Bus

I

The I

2

C Status and Control register bits are defined in Table 14-1, with a more detailed description following.

11

24 Bits: P3[7:0], P1[7:0], P0[7:0]

10

16 Bits: P1[7:0], P0[7:0]

01

8 Bits: P0[7:0]

00

No HAPI Interface

X

1

I

2

C on P2[1:0], 0:SCL, 1:SDA

0

0

I

2

C on P1[1:0], 0:SCL, 1:SDA

1

0

I

2

C on P2[1:0], 0:SCL, 1:SDA

7

6

5

4

3

2

1

0

 I

2

C Data 7

 I

2

C Data 6

 I

2

C Data 5

 I

2

C Data 4

 I

2

C Data 3

 I

2

C Data 2

 I

2

C Data 1

 I

2

C Data 0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

X

X

X

X

X

X

X

X

7

6

5

4

3

2

1

0

MSTR Mode

Continue/Busy

Xmit Mode

ACK

Addr

ARB 

Lost/Restart

Received Stop

I

2

C Enable

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

0

0

0

0

0