Cypress CY8C24123A Manual De Usuario
CY8C24123A
CY8C24223A, CY8C24423A
Document Number: 38-12028 Rev. *I
Page 10 of 56
28-Pin Part Pinout
Table 5. Pin Definitions - 28-Pin PDIP, SSOP, and SOIC
Pin
No.
No.
Type
Pin
Name
Description
Figure 7. CY8C24423A 28-Pin PSoC Device
Digital Analog
1
IO
I
P0[7]
Analog Column Mux Input
2
IO
IO
P0[5]
Analog Column Mux Input and column
output
output
3
IO
IO
P0[3]
Analog Column Mux Input and Column
Output
Output
4
IO
I
P0[1]
Analog Column Mux Input
5
IO
P2[7]
6
IO
P2[5]
7
IO
I
P2[3]
Direct Switched Capacitor Block Input
8
IO
I
P2[1]
Direct Switched Capacitor Block Input
9
Power
SMP
Switch Mode Pump (SMP) Connection to
External Components required
External Components required
10
IO
P1[7]
I2C Serial Clock (SCL)
11
IO
P1[5]
I2C Serial Data (SDA)
12
IO
P1[3]
13
IO
P1[1]
Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*
(SCL), ISSP-SCLK*
14
Power
Vss
Ground connection.
15
IO
P1[0]
Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*
(SDA), ISSP-SDATA*
16
IO
P1[2]
17
IO
P1[4]
Optional External Clock Input (EXTCLK)
18
IO
P1[6]
19
Input
XRES Active High External Reset with Internal
Pull Down
20
IO
I
P2[0]
Direct Switched Capacitor Block Input
21
IO
I
P2[2]
Direct Switched Capacitor Block Input
22
IO
P2[4]
External Analog Ground (AGND)
23
IO
P2[6]
External Voltage Reference (VRef)
24
IO
I
P0[0]
Analog Column Mux Input
25
IO
I
P0[2]
Analog Column Mux Input
26
IO
I
P0[4]
Analog Column Mux Input
27
IO
I
P0[6]
Analog Column Mux Input
28
Power
Vdd
Supply Voltage
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Pro-
grammable Sytem-on-Chip Technical Reference Manual for details.
grammable Sytem-on-Chip Technical Reference Manual for details.
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
P2[5]
A, I, P2[3]
A, I, P2[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
Vdd
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
P2[6], External VRef
P2[4], External AGND
P2[2], A, I
P2[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
P2[6], External VRef
P2[4], External AGND
P2[2], A, I
P2[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
PDIP
SSOP
SOIC
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
10
11
12
13
14
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
27
26
25
24
23
22
21
20
19
18
17
16
15