Cypress CY8C24123A Manual De Usuario
CY8C24123A
CY8C24223A, CY8C24423A
Document Number: 38-12028 Rev. *I
Page 9 of 56
20-Pin Part Pinout
Table 4. Pin Definitions - 20-Pin PDIP, SSOP, and SOIC
Pin
No.
No.
Type
Pin
Name
Description
Figure 6. CY8C24223A 20-Pin PSoC Device
Digital
Analog
1
IO
I
P0[7]
Analog Column Mux Input
2
IO
IO
P0[5]
Analog Column Mux Input and Column
Output
Output
3
IO
IO
P0[3]
Analog Column Mux Input and Column
Output
Output
4
IO
I
P0[1]
Analog Column Mux Input
5
Power
SMP
Switch Mode Pump (SMP) Connection to
External Components required
External Components required
6
IO
P1[7]
I2C Serial Clock (SCL)
7
IO
P1[5]
I2C Serial Data (SDA)
8
IO
P1[3]
9
IO
P1[1]
Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*
(SCL), ISSP-SCLK*
10
Power
Vss
Ground Connection.
11
IO
P1[0]
Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*
(SDA), ISSP-SDATA*
12
IO
P1[2]
13
IO
P1[4]
Optional External Clock Input (EXTCLK)
14
IO
P1[6]
15
Input
XRES Active High External Reset with Internal
Pull Down
16
IO
I
P0[0]
Analog Column Mux Input
17
IO
I
P0[2]
Analog Column Mux Input
18
IO
I
P0[4]
Analog Column Mux Input
19
IO
I
P0[6]
Analog Column Mux Input
20
Power
Vdd
Supply Voltage
LEG
END: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details.
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, IO, P0[3]
A, I, P0[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
PDIP
SSOP
SOIC
20
19
18
17
16
15
14
13
12
11
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
10
Vdd
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA