Cypress CY7C65113C Manual De Usuario

Document #: 38-08002  Rev. *D

Page 25 of 49

During a reset, the contents of the Global Interrupt Enable Register and USB End Point Interrupt Enable Register are cleared,

effectively disabling all interrupts,
The interrupt controller contains a separate flip-flop for each interrupt. See Figure 14-3 for the logic block diagram of the interrupt

controller. When an interrupt is generated, it is first registered as a pending interrupt. It stays pending until it is serviced or a reset

occurs. A pending interrupt only generates an interrupt request if it is enabled by the corresponding bit in the interrupt enable

registers. The highest priority interrupt request is serviced following the completion of the currently executing instruction.
When servicing an interrupt, the hardware does the following:

1. Disables all interrupts by clearing the Global Interrupt Enable bit in the CPU (the state of this bit can be read at Bit 2 of the 

Processor Status and Control Register, Figure 13-1). 

2. Clears the flip-flop of the current interrupt. 
3. Generates an automatic CALL instruction to the ROM address associated with the interrupt being serviced (i.e., the Interrupt 

Vector, see Section 14.1). 

The instruction in the interrupt table is typically a JMP instruction to the address of the Interrupt Service Routine (ISR). The user

can reenable interrupts in the interrupt service routine by executing an EI instruction. Interrupts can be nested to a level limited

only by the available stack space.
The Program Counter value as well as the Carry and Zero flags (CF, ZF) are stored onto the Program Stack by the automatic

CALL instruction generated as part of the interrupt acknowledge process. The user firmware is responsible for ensuring that the

processor state is preserved and restored during an interrupt. The PUSH A instruction should typically be used as the first

command in the ISR to save the accumulator value and the POP A instruction should be used to restore the accumulator value

just before the RETI instruction. The program counters CF and ZF are restored and interrupts are enabled when the RETI

instruction is executed.
The IDI and EI instruction can be used to disable and enable interrupts, respectively. These instruction affect only the Global

Interrupt Enable bit of the CPU. If desired, EI can be used to re-enable interrupts while inside an ISR, instead of waiting for the

RETI that exits the ISR. While the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by

examining the IRQ Sense bit (Bit 7 in the Processor Status and Control Register).

The Interrupt Vectors supported by the USB Controller are listed in Table 14-1. The lowest-numbered interrupt (USB Bus Reset

interrupt) has the highest priority, and the highest-numbered interrupt (I

2

C interrupt) has the lowest priority. 

 

µs CLR

µs IRQ