Cypress CY7C65113C Manual De Usuario

Document #: 38-08002  Rev. *D

Page 27 of 49

There are five USB endpoint interrupts, one per endpoint. A USB endpoint interrupt is generated after the USB host writes to a

USB endpoint FIFO or after the USB controller sends a packet to the USB host. The interrupt is generated on the last packet of

the transaction (e.g., on the host’s ACK on an IN transfer, or on the device ACK on an OUT transfer). If no ACK is received during

an IN transaction, no interrupt is generated.

A USB hub interrupt is generated by the hardware after a connect/disconnect change, babble, or a resume event is detected by

the USB repeater hardware. The babble and resume events are additionally gated by the corresponding bits of the Hub Port

Enable Register (Figure 16-3). The connect/disconnect event on a port does not generate an interrupt if the SIE does not drive

the port (i.e., the port is being forced).

Each of the GPIO pins can generate an interrupt, if enabled. The interrupt polarity can be programmed for each GPIO port as

part of the GPIO configuration. All of the GPIO pins share a single interrupt vector, which means the firmware needs to read the

GPIO ports with enabled interrupts to determine which pin or pins caused an interrupt. A block diagram of the GPIO interrupt

logic is shown in Figure 14-4.

. 

Refer to Sections 9.1 and 9.2 for more information of setting GPIO interrupt polarity and enabling individual GPIO interrupts. If

one port pin has triggered an interrupt, no other port pins can cause a GPIO interrupt until that port pin has returned to its inactive

(non-trigger) state or its corresponding port interrupt enable bit is cleared. The USB Controller does not assign interrupt priority

to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process. 

The I

2

C interrupt occurs after various events on the I

2

C-compatible bus to signal the need for firmware interaction. This generally

involves reading the I

2

C Status and Control Register (Figure 12-2) to determine the cause of the interrupt, loading/reading the

I

2

C Data Register as appropriate, and finally writing the Processor Status and Control Register (Figure 13-1) to initiate the

subsequent transaction. The interrupt indicates that status bits are stable and it is safe to read and write the I

2

C registers. Refer

to Section 12.0 for details on the I

2

C registers.

When enabled, the I

2

C-compatible state machines generate interrupts on completion of the following conditions. The referenced

bits are in the I

2

C Status and Control Register.

1. In slave receive mode, after the slave receives a byte of data: The Addr bit is set, if this is the first byte since a start or restart 

signal was sent by the external master. Firmware must read or write the data register as necessary, then set the ACK, Xmit 

MODE, and Continue/Busy bits appropriately for the next byte.

2. In slave receive mode, after a stop bit is detected: The Received Stop bit is set, if the stop bit follows a slave receive transaction 

where the ACK bit was cleared to 0, no stop bit detection occurs.