Cypress CY62147EV30 Manual De Usuario

Document #: 38-05440 Rev. *G

Page 3 of 13

Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.

Storage Temperature  ................................ –65°C to + 150°C

Ambient Temperature with
Power Applied  .......................................... –55°C to + 125°C

Supply Voltage to Ground 
Potential ............................. –0.3V to + 3.9V (V

CCmax 

+ 0.3V)

DC Voltage Applied to Outputs
in High-Z State 

[5, 6]

............... –0.3V to 3.9V (V

CCmax 

+ 0.3V)

DC Input Voltage 

............ –0.3V to 3.9V (V

CCmax 

+ 0.3V)

Output Current into Outputs (LOW) ............................ 20 mA

Static Discharge Voltage ..........................................  >2001V
(MIL-STD-883, Method 3015)

Latch Up Current ..................................................... >200 mA

CY62147EV30LL

Ind’l/Auto-A –40°C to +85°C 

2.2V to 

3.6V

Auto-E

–40°C to +125°C 

Over the Operating Range

[2]

V

OH

Output HIGH 
Voltage

I

OH

 = –0.1 mA 

2.0

2.0

V

I

OH

 = –1.0 mA, V

CC 

> 2.70V

2.4

2.4

V

V

OL

Output LOW 
Voltage

I

OL

 = 0.1 mA

0.4

0.4

V

I

OL

 = 2.1 mA, V

CC 

= 2.70V 

0.4

0.4

V

V

IH

Input HIGH 
Voltage

V

CC 

= 2.2V to 2.7V

1.8

V

CC 

+ 0.3

1.8

V

CC 

+ 0.3

V

V

CC

= 2.7V to 3.6V

2.2

V

CC 

+ 0.3

2.2

V

CC 

+ 0.3

V

V

IL

Input LOW 
Voltage

V

CC 

= 2.2V to 2.7V

–0.3

0.6

–0.3

0.6

V

V

CC

= 2.7V to 3.6V

–0.3

0.8

–0.3

0.8

V

I

IX

Input Leakage 
Current

GND < V

I

 < V

CC

–1

+1

–4

+4

μA

I

OZ

Output Leakage 
Current

GND < V

O 

< V

CC

, Output Disabled

–1

+1

–4

+4

μA

I

CC

V

CC

 Operating 

Supply Current 

f = f

max

 = 1/t

RC

V

CC

 = V

CC(max)

I

OUT

 = 0 mA

CMOS levels

15

20

15

25

mA

f = 1 MHz

2

2.5

2

3

I

SB1

Automatic CE
Power Down 
Current — 
CMOS Inputs

CE > V

CC

 – 0.2V 

V

IN

 > V

CC 

– 0.2V, V

IN

 < 0.2V

f = f

max

 (Address and Data Only),

 f = 0 (OE, BHE, BLE and WE), 
V

CC

 = 3.60V

1

7

1

20

μA

I

SB2 

Automatic CE 
Power Down 
Current — 
CMOS Inputs

CE > V

CC

 – 0.2V

V

IN

 > V

CC

 – 0.2V or V

IN

 < 0.2V,

f = 0, V

CC

 = 3.60V

1

7

1

20

μA

 

For all packages.

C

IN

Input Capacitance

T

A

 = 25°C, f = 1 MHz,

V

CC

 = V

CC(typ)

10

pF

C

OUT

Output Capacitance

10

pF

5. V

IL(min)

 = –2.0V for pulse durations less than 20 ns.

6. V

IH(max) 

= V

CC 

+ 0.75V for pulse durations less than 20 ns.

7. Full device AC operation assumes a minimum of 100 

μs ramp time from 0 to V

CC

(min) and 200 

μs wait time after V

CC 

stabilization.

8. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I

SB2

 / I

CCDR 

spec. Other inputs can be left floating.

9. Tested initially and after any design or process changes that may affect these parameters.