Cypress CY7C1443AV33 Manual De Usuario
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Document #: 38-05357 Rev. *G
Page 8 of 31
DQ
s
IO-
Synchronous
Bidirectional Data IO lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by the addresses presented during
the previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH,
DQ
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by the addresses presented during
the previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH,
DQ
s
and DQP
X
are placed in a tri-state condition.The outputs are automati-
cally tri-stated during the data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
DQP
X
IO-
Synchronous
Bidirectional Data Parity IO Lines. Functionally, these signals are identical
to DQ
to DQ
s
.
During write sequences, DQP
x
is controlled by BW
[A:H]
correspond-
ingly.
MODE
Input-Static
Selects Burst Order. When tied to GND selects linear burst sequence. When
tied to V
tied to V
DD
or left floating selects interleaved burst sequence. This is a strap
pin and should remain static during device operation. Mode Pin has an internal
pull up.
pull up.
V
DD
Power Supply
Power Supply Inputs to the Core of the Device.
V
DDQ
IO Power Supply
Power Supply for the IO Circuitry.
V
SS
Ground
Ground for the Core of the Device.
V
SSQ
IO Ground
Ground for the IO Circuitry.
TDO
JTAG serial output
Synchronous
Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of
TCK. If the JTAG feature is not being utilized, this pin should be left uncon-
nected. This pin is not available on TQFP packages.
TCK. If the JTAG feature is not being utilized, this pin should be left uncon-
nected. This pin is not available on TQFP packages.
TDI
JTAG serial
input
Synchronous
Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If
the JTAG feature is not being utilized, this pin can be left floating or connected
to V
the JTAG feature is not being utilized, this pin can be left floating or connected
to V
DD
through a pull up resistor. This pin is not available on TQFP packages.
TMS
JTAG serial
input
Synchronous
Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If
the JTAG feature is not being utilized, this pin can be disconnected or
connected to V
the JTAG feature is not being utilized, this pin can be disconnected or
connected to V
DD
. This pin is not available on TQFP packages.
TCK
JTAG-Clock
Clock Input to the JTAG Circuitry. If the JTAG feature is not being utilized,
this pin must be connected to V
this pin must be connected to V
SS
. This pin is not available on TQFP
packages.
NC
-
No Connects. Not internally connected to the die. 72M, 144M and 288M are
address expansion pins are not internally connected to the die.
address expansion pins are not internally connected to the die.
NC/72M, NC/144M,
NC/288M, NC/576M
NC/1G
NC/288M, NC/576M
NC/1G
-
No Connects. Not internally connected to the die. NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins are not internally
connected to the die.
NC/288M, NC/576M and NC/1G are address expansion pins are not internally
connected to the die.
Pin Definitions
(continued)
Name
IO
Description