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Cypress CY7C1441AV33 Manual De Usuario

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CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Document #: 38-05357 Rev. *G
Page 24 of 31
Figure 5.  Read/Write Cycle Timing
.
Timing Diagrams
 (continued)
tCYC
t
CL
CLK
tADH
tADS
ADDRESS
t
CH
tAH
tAS
A2
tCEH
tCES
Single WRITE
D(A3)
A3
A4
BURST READ
Back-to-Back READs
High-Z
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
t
WEH
t
WES
t
OEHZ
tDH
tDS
tCDV
tOELZ
A1
A5
A6
D(A5)
D(A6)
Q(A1)
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
ADSP
ADSC
BWE, BW
X
CE
ADV
OE
Data In (D)
Data Out (Q)
Note
26. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
27. GW is HIGH