Cypress CY7C2561KV18 Manual De Usuario

Document Number: 001-15887 Rev. *E

Page 7 of 29

K

Input Clock

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device 

and to drive out data through Q

[x:0]

. All accesses are initiated on the rising edge of K. 

K

Input Clock

Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and 

to drive out data through Q

[x:0]

.

CQ

Echo Clock

Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock 

(K) of the QDR-II+. The timings for the echo clocks are shown in the 

CQ

Echo Clock

Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock 

(K) of the QDR-II+.The timings for the echo clocks are shown in the 

ZQ

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus 

impedance. CQ, CQ, and Q

[x:0] 

output impedance are set to 0.2 x RQ, where RQ is a resistor connected 

between ZQ and ground. Alternatively, this pin can be connected directly to V

DDQ

, which enables the 

minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

DOFF

Input

− Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings 

in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin 

can be connected to a pull up through a 10 K

Ω or less pull up resistor. The device behaves in QDR-I 

mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 

MHz with QDR-I timing. 

TDO

Output

TDO for JTAG.

TCK

Input

TCK Pin for JTAG.

TDI

Input

TDI Pin for JTAG.

TMS

Input

TMS Pin for JTAG.

NC

N/A

Not Connected to the Die. Can be tied to any voltage level.

NC/144M

N/A

Not Connected to the Die. Can be tied to any voltage level.

NC/288M

N/A

Not Connected to the Die. Can be tied to any voltage level.

V

REF

Input-

Reference

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC 

measurement points.

V

DD

Power Supply Power Supply Inputs to the Core of the Device. 

V

SS

Ground

Ground for the Device. 

V

DDQ

Power Supply Power Supply Inputs for the Outputs of the Device.

Table 2.  Pin Definitions  (continued)