Fujitsu FR81S Manual De Usuario
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
19
4.1.1.
Serial Mode Register: SMR
This register selects the serial communication method (UART or I
2
C). Bits 3 to 0 change their function
according to the method selected (UART, CSIO, or I
2
C).
SMRn (n= 0 to 11): Address Base addr + 01
H
(Access: Byte, Half-word, Word)
7
6
5
4
3
2
1
0
bit
MD[2:0]
Reserved
SBL/
SCINV/
RIE
BDS/TIE SCKE/
(Reserved)
SOE/
(Reserved)
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(R/W0)
R/W
(R/W0)
Attribute
[bit7 to bIt5] MD[2:0] (MoDe): Operation mode
These bits are used to set the communication method.
"000
B
": Operating mode 0 (asynchronous normal mode) is set.
"001
B
": Operating mode 1 (asynchronous multi-processor mode) is set.
"010
B
": Operating mode 2 (CSIO mode) is set.
"011
B
": Operating mode 3 (LIN communication mode) is set.
"100
B
": Operating mode 4 (I
2
C mode) is set.
Notes:
⋅
Settings other than those listed above are prohibited.
⋅
Configure each register after setting the operation mode.
⋅
[UART][CSIO][LIN-UART] Before changing the operation mode, execute programmable clear
(SCR:UPCL=1).
⋅
[I
2
C] Before changing the operation mode, disable I
2
C (ISMK:EN=0).
⋅
Only ch.2 does not have I
2
C function.
[bit4] Reserved
Writing/reading does not affect the operation.
[bit3] SBL/SCINV/RIE (Stop Bit Length/Serial Clock Inversion/Receive Interrupt Enable): Stop bit
length selection bit/serial clock inversion bit, reception interrupt enable bit
[UART][LIN-UART]
This bit configures the bit length of stop bit (frame end mark for transmission data):
When SBL="0" and ESCR:ESBL="0" are set: Stop bit is set to 1 bit.
When SBL="1" and ESCR:ESBL="0" are set: Stop bit is set to 2 bits.
When SBL="0" and ESCR:ESBL="1" are set: Stop bit is set to 3 bits.
When SBL="1" and ESCR:ESBL="1" are set: Stop bit is set to 4 bits.
Notes:
⋅
When receiving, only the first bit of the stop bits will always be detected.
⋅
This bit should be set when transmission is disabled (TXE=0).
[CSIO]
This bit inverts the serial clock format. When chip select is used in master mode (SCR: MS=0), this bit is
used for serial chip select pin 0 communication.
MB91520 Series
MN705-00010-1v0-E
1332