SMSC LAN1198 Manual De Usuario

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LAN9118 Family Programmer Reference Guide
Revision 1.0 (12-14-09)
2
SMSC AN 12.12
APPLICATION NOTE
 
„
An octet or byte is a group of 8 bits, treated as a single unit, with a value of 0-255 unsigned, or -
127 to +127 signed. A byte is generally the smallest unit of data that can be individually addressed.
„
A word or short int is a group of 16 bits or two bytes,2 adjacent bytes, representing a 16-bit, single 
symbol or a numeric range from 0 – 65,535 unsigned, or +/- 32,767 as a signed value.  WORD 
values are aligned on 2-byte memory boundaries.  Their addresses are always expressed in even 
number terms ending in 0x0, 0x2, 0x4, 0x6, 0x8, 0xa, 0xc, and 0xe.
„
A DWORD or long int always refers to 4 adjacent bytes, representing a 32-bit, single symbol or a 
numeric range from 0 – 4,294,967,295, or +/- 2,147,483,647 as a signed value.  DWORD values 
are aligned on 4-byte memory boundaries.  Their addresses are always expressed in even number 
terms ending in 0x0, 0x4, 0x8, and 0xc.
2 Controller Overview
LAN9118 Family devices are full-featured, single-chip 10/100 Ethernet controllers designed for
embedded applications where performance, flexibility, ease of integration and low cost are required.
LAN9118 Family devices are fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant.
LAN9118 Family devices include an integrated Ethernet MAC and PHY with a high-performance
SRAM-like slave interface. The simple, yet highly functional host bus interface provides glue-less
connection to most common 32- and 16-bit microprocessors and microcontrollers, including those 32-
bit microprocessors presenting a 16-bit data bus interface to the device. LAN9118 Family Devices
include large transmit and receive data FIFOs with a high-speed host bus interface to accommodate
high bandwidth, high latency applications. In addition, the devices memory buffer architecture allows
the most efficient use of memory resources by optimizing packet granularity.
2.1   Block Diagrams
2.1.1   Internal Block Diagram
Figure 2.1 LAN9118 Family Device Internal Block Diagram
10/100 Ethernet
PHY
10/100 Ethernet MAC
2kB to 14kB
Configurable TX FIFO
2kB to 14kB
Configurable  RX FIFO
Host Bus Interface
(HBI)
SRAM I/F
Interrupt
Controller
GP Timer
PIO Controller
IRQ
FIFO_SEL
+3.3V to +1.8V
PLL Regulator
PLL
25MHz
+3.3V
EEPROM
Controller
EEPROM
(Optional)
RX Status FIFO
TX Status FIFO
MIL - TX Elastic
Buffer - 2K
MIL - RX Elastic
Buffer - 128bytes
+3.3V to +1.8V
Core Regulator
+3.3V