Manual De UsuarioTabla de contenidos1 Introduction11.1 References11.2 Document Conventions12 Controller Overview22.1 Block Diagrams22.1.1 Internal Block Diagram2Figure 2.1 LAN9118 Family Device Internal Block Diagram22.1.2 System Level Block Diagram3Figure 2.2 LAN9118 Family Device System-Level Block-Diagram32.2 Common Product Family Features33 Register Description5Figure 3.1 LAN9118 Family Device Memory MAP53.1 Directly Addressable Registers6Table 3.1 LAN9118 Family Directly Addressable Register Map63.2 MAC Control and Status Registers7Table 3.2 LAN9118 Family MAC CSR Register Map73.3 PHY Registers7Table 3.3 LAN9118 Family PHY Control and Status Register83.4 Restrictions on Read-Follow-Write CSR Accesses8Table 3.4 Read after Write Timing Rules93.5 Restrictions on Read-Follow-Read CSR Accesses9Table 3.5 Special Back-to-Back Cycles104 Programming Recommendations104.1 The Necessity of Register Ownership104.2 The Importance of Planning (strcmp(“Fail to Plan”) == strcmp (“Plan to Fail”))104.3 Orthogonal Register Set104.4 Register Functionality in the LAN9118 Family Devices11Table 4.1 Independent Data Threads Register Usage114.5 An Example of Concurrency124.6 Software Interrupt Feature (SwInt)124.7 Ownership Policy in the Simple Driver13Table 4.2 Register Ownership Policy in the Simple Driver135 Initialization155.1 MAC Initialization155.1.1 Software Reset of the MAC155.1.2 FIFO Allocation and Flow-Control Configuration155.1.3 Setting the MAC Address15Table 5.1 EEPROM MAC Address Layout165.2 Configuring Interrupts165.2.1 Configuring the IRQ Pin165.2.2 Setting The Interrupt De-assertion Period165.2.3 Enabling and Disabling Interrupts165.3 Stopping and Starting the Transmitter175.4 Stopping and Starting the Receiver175.5 Configuring Address Filtering Options18Table 5.2 Address Filtering Modes185.5.1 Configuring Multicast Filtering185.5.2 Promiscuous Mode185.6 PHY Detection and Initialization19Table 5.3 Using the MAC_CSR_CMD Register to Access the MII_ACC Register19Table 5.4 Using the MAC_CSR_CMD Register to Access the MII_DATA Register19Table 5.5 Media Independent Interface Access/Command Register20Figure 5.1 PHY Access Command and Data Pathways215.7 Switching Between Internal and External PHYs22Figure 5.2 The MII Switching Procedure235.8 Examples of PHY MII Register Reads and Writes246 Transmit Packet Processing276.1 Transmit Data Transfer276.2 Command Word Construction276.3 Per Packet Flow Control286.4 Packet Transfer Completion: Management Statistics29Table 6.1 ransmit Status Word296.5 Transmit Packet Examples30Table 6.2 Transmit Packet Example30Table 6.3 Buffer End Alignment30Table 6.4 Transmit Command Words31Table 6.5 Single Buffer Single Packet Data Transfer Sequence31Figure 6.1 Multiple (3) Buffer Data Single Packet Transfer Sequence326.5.1 Transmit Command Words for Figure 6.1, "Multiple (3) Buffer Data Single Packet Transfer Sequence"33Table 6.6 TX_CMD_A for Segment 133Table 6.7 TX_CMD_B for Segment 133Table 6.8 TX_CMD_A for Segment 233Table 6.9 TX_CMD_B for Segment 233Table 6.10 TX_CMD_A for Segment 333Table 6.11 TX_CMD_B for Segment 333Table 6.12 Multiple (3) Packet Data Transfer Sequence346.6 The Overall Packet Transmit Process34Figure 6.2 Packet Transmission357 Receive Packet Processing36Table 7.1 Receive Status Word36Figure 7.1 Packet Reception377.1 Receive Data Transfer38Table 7.2 Receive Data Buffer Example38Table 7.3 RX End Alignment39Table 7.4 Receiver Configuration Word397.2 Purging Receive Packets397.3 Flow Control Function407.3.1 Backpressure407.3.2 Pause Frames408 Instrumentation and Debug418.1 Debug Prints418.1.1 SMSC_TRACE(message, parameters)418.1.2 SMSC_WARNING(message, parameters)418.1.3 SMSC_ASSERT(condition)428.2 GPIO pins in Conjunction with Oscilloscope42Figure 8.1 Oscilloscope/Logic Analyzer Display438.3 TxCLK and RxCLK438.4 Error Interrupts are Invaluable Tools438.5 Integrating the Driver: Early Testing449 Power Management Events449.1 System Description44Tamaño: 600 KBPáginas: 45Language: EnglishManuales abiertas