SMSC LAN1198 Manual De Usuario
LAN9118 Family Programmer Reference Guide
Revision 1.0 (12-14-09)
38
SMSC AN 12.12
APPLICATION NOTE
7.1 Receive Data Transfer
Given that the device makes all data transfers in DWORD pieces, the driver can easily align the
receiving data memory address to a DWORD boundary. Recall too, that the data transfer length must
also be rounded up when considering overall data buffer length (i.e., a 109-byte packet should be
treated as a 4*28 or 112 byte transfer).
receiving data memory address to a DWORD boundary. Recall too, that the data transfer length must
also be rounded up when considering overall data buffer length (i.e., a 109-byte packet should be
treated as a 4*28 or 112 byte transfer).
The RX Data Offset field gives the driver control over packet alignment
Commonly, TCP/IP based protocol stacks optimize packet data access by aligning the start of the IP
header to a DWORD boundary. Using the example RX Status of an 89-byte packet shown in
header to a DWORD boundary. Using the example RX Status of an 89-byte packet shown in
just above is a packet buffer starting at 0xb4002000, and it shows where we want the data to wind up
after the transfer is complete, The data buffer is aligned on a 32-byte boundary, and contains an IP
version 4 style packet, with a header length of 5 DWORDS (0x45), After the transfer, the beginning
of the IP header portion, the byte containing the value 0x45 is aligned at physical address 0xb4002020.
As the MAC header which precedes it in memory is 14 bytes in length (6-byte destination address, 6-
byte source address, 2-byte packet type/length), adding an 18-byte offset to the start of where the
driver stores this packet, will align the IP header on the next 32-byte boundary (14+18 == 32). For
this example we will be working with a DMA controller capable of 32-byte cache line burst transfers,
hence the need for RX End Alignment. It is necessary for the driver to inform the device of the DMA
controllers burst ability because the burst addressing will cause additional reads to be generated to
the device even though no data may actually be transferred at the end of the packet transfer. Hence
the need for padding the packet memory buffer to the alignment indicated by this field
after the transfer is complete, The data buffer is aligned on a 32-byte boundary, and contains an IP
version 4 style packet, with a header length of 5 DWORDS (0x45), After the transfer, the beginning
of the IP header portion, the byte containing the value 0x45 is aligned at physical address 0xb4002020.
As the MAC header which precedes it in memory is 14 bytes in length (6-byte destination address, 6-
byte source address, 2-byte packet type/length), adding an 18-byte offset to the start of where the
driver stores this packet, will align the IP header on the next 32-byte boundary (14+18 == 32). For
this example we will be working with a DMA controller capable of 32-byte cache line burst transfers,
hence the need for RX End Alignment. It is necessary for the driver to inform the device of the DMA
controllers burst ability because the burst addressing will cause additional reads to be generated to
the device even though no data may actually be transferred at the end of the packet transfer. Hence
the need for padding the packet memory buffer to the alignment indicated by this field
Table 7.2 Receive Data Buffer Example
PHYSICAL MEMORY
0XB
400
200
0
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0xc
0xd
0xe
0xf
0x0
0
0x1
0
00
0e
83
a0
de
ff
00
80
0f
71
55
71
08
00
0x2
0
45
00
00
28
11
56
40
00
80
06
f0
6a
aa
81
50
76
0x3
0
aa
81
53
96
04
e7
01
bd
a9
4a
38
0d
0a
d6
7c
6c
0x4
0
50
10
ff
ff
f9
29
00
00
66
6f
72
53
4d
53
43
4d
0x5
0
2e
20
44
62
76
69
64
20
47
65
4c
62
6d
61
6e
20
0x6
0
77
72
6f
74
65
20
74
68
69
73
2e
0x7
0
0x8
0