SMSC LAN9420 Manual De Usuario
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
99
Revision 1.22 (09-25-08)
DATASHEET
4.2.11
EEPROM Command Register (E2P_CMD)
This register is used to control the read and write operations with the serial EEPROM.
Offset:
00F8h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31
EPC Busy (EPC_BSY)
When a 1 is written into this bit, the operation specified in the EPC command
field is performed at the specified EEPROM address. This bit will remain set
until the operation is complete. In the case of a read this means that the Host
can read valid data from the E2P data register. The E2P_CMD and
E2P_DATA registers should not be modified until this bit is cleared. In the
case where a write is attempted and an EEPROM is not present, the EPC
Busy remains busy until the EPC Time-out occurs. At that time the busy bit
is cleared.
When a 1 is written into this bit, the operation specified in the EPC command
field is performed at the specified EEPROM address. This bit will remain set
until the operation is complete. In the case of a read this means that the Host
can read valid data from the E2P data register. The E2P_CMD and
E2P_DATA registers should not be modified until this bit is cleared. In the
case where a write is attempted and an EEPROM is not present, the EPC
Busy remains busy until the EPC Time-out occurs. At that time the busy bit
is cleared.
Note:
EPC busy will be high immediately following power-up or reset.
After the EEPROM controller has finished reading (or attempting to
read) the MAC address and SSVID/SSID from the EEPROM, the
EPC Busy bit is cleared.
After the EEPROM controller has finished reading (or attempting to
read) the MAC address and SSVID/SSID from the EEPROM, the
EPC Busy bit is cleared.
SC
0b