Renesas M34571T2-CPE Manual De Usuario
M34571T2-CPE User’s Manual
4. Hardware Specifications
REJ10J0972-0100 Rev.1.00 February 10, 2006
Page 64 of 72
IMPORTANT
Note on the RAM Backup Mode:
Although this emulator allows you to execute a program using POF instructions, execution of such programs is
subject to the following limitations:
subject to the following limitations:
The POF instruction cannot be stepped and over-stepped. Therefore, do not attempt to step and step-over the
POF instruction.
POF instruction.
No events (hardware breaks and trace points) can be set in execution cycles of the POF instruction. The events
set in execution cycles of the POF instruction, if any, have no effect.
set in execution cycles of the POF instruction, if any, have no effect.
During RAM backup mode, no commands of the emulator debugger M3T-PD45M except for RESET can be
executed. Exit RAM backup mode by applying key-on wakeup input or reset input before executing the
commands.
executed. Exit RAM backup mode by applying key-on wakeup input or reset input before executing the
commands.
Note on the MCU Status While the Program is Idle:
The MCU status while the program is idle show below.
DI insertion mode: DI insertion mode is executed while the user program has stopped.
Clock stop mode: Clock stops while the user program has stopped.
Clock stop mode: Clock stops while the user program has stopped.
* In this status, the timer and other internal peripheral functions are stopped. However, if the internal RAM
reference/setting, Register reference/setting, step execution, etc. are performed, a clock is supplied.
reference/setting, Register reference/setting, step execution, etc. are performed, a clock is supplied.
Note on a Break Operation When Skipping Instructions
In cases when the next instruction is skipped by a skip instruction, if a break operation (hardware, software or
forcible break) in the skipped instruction is attempted, no break occurs. If a skip and a break occur at the same
time, the cause of the break is cleared and the program continues running until the next cause of break occurs.
Example: If a break operation is attempted when executing an instruction at address 0002, the intended break
forcible break) in the skipped instruction is attempted, no break occurs. If a skip and a break occur at the same
time, the cause of the break is cleared and the program continues running until the next cause of break occurs.
Example: If a break operation is attempted when executing an instruction at address 0002, the intended break
is canceled and the program continues running.
[ADDR] [CODE]
0000 RC
0001 SZC
0002 TABP 1 :
0001 SZC
0002 TABP 1 :
Skipped instruction
0003 TAM
0004 BL
0004 BL
0004 :
The program continues to execute
instruction without breaking.
Note on a Break Operation in a Train of Successive Instructions:
The program does not break in a train of successive instructions. If a break operation (hardware, software or
forcible break) is attempted in a train of successive instructions, the intended break occurs in an instruction at
which the successive instructions ended. An example is shown below.
Example: If a break operation is attempted while executing the instructions at addresses 0000--0003, the break
forcible break) is attempted in a train of successive instructions, the intended break occurs in an instruction at
which the successive instructions ended. An example is shown below.
Example: If a break operation is attempted while executing the instructions at addresses 0000--0003, the break
occurs at address 0004.
[ADDR] [CODE]
0000 LA 0
0001 LA 1
0002 LA 2
0003 LA 3
0004 NOP < A break occurs at this address.
0000 LA 0
0001 LA 1
0002 LA 2
0003 LA 3
0004 NOP < A break occurs at this address.
Successive instructions