Renesas HD6417641 Manual De Usuario
Section 4 Clock Pulse Generator (CPG)
Rev. 4.00 Sep. 14, 2005 Page 147 of 982
REJ09B0023-0400
Mode 2: The frequency of the signal received from the EXTAL pin or crystal resonator LSI is
quadrupled by the PLL circuit 2 before it is supplied as the clock signal. This lowers the frequency
required of the externally generated clock. Either a crystal resonator with a frequency in the range
from 10 to 12.5 MHz or an external signal in the same frequency range input on the EXTAL pin
may be used. The frequency range of CKIO is from 40 to 50 MHz.
quadrupled by the PLL circuit 2 before it is supplied as the clock signal. This lowers the frequency
required of the externally generated clock. Either a crystal resonator with a frequency in the range
from 10 to 12.5 MHz or an external signal in the same frequency range input on the EXTAL pin
may be used. The frequency range of CKIO is from 40 to 50 MHz.
Mode 6: The frequency of the signal received from the EXTAL pin or crystal resonator LSI is
doubled by the PLL circuit 2 before it is supplied as the clock signal. This lowers the frequency
required of the crystal resonator. A crystal resonator or an external signal with a frequency in the
range from 10 to 25 MHz may be used. The frequency range of CKIO is from 20 to 50 MHz.
doubled by the PLL circuit 2 before it is supplied as the clock signal. This lowers the frequency
required of the crystal resonator. A crystal resonator or an external signal with a frequency in the
range from 10 to 25 MHz may be used. The frequency range of CKIO is from 20 to 50 MHz.
Mode 7: In this mode, the CKIO pin functions as an input pin. An external clock signal is
supplied to this pin; after this signal is received, the PLL circuit 1 shapes its waveform and
multiplies its frequency. The resulting clock signal is then supplied within the LSI. For reduced
current and hence power consumption, pull up the EXTAL pin and open the XTAL pin when the
LSI is used in mode 7.
supplied to this pin; after this signal is received, the PLL circuit 1 shapes its waveform and
multiplies its frequency. The resulting clock signal is then supplied within the LSI. For reduced
current and hence power consumption, pull up the EXTAL pin and open the XTAL pin when the
LSI is used in mode 7.
Table 4.3
Relationship between Clock Mode and Frequency Range
PLL frequency
multiplier Selectable
frequency ranges (MHz)
Clock
operating
mode
FRQCR
register
setting
PLL
Circuit 1
PLL
Circuit 2
Ratio of internal
clock frequencies
(I:B:P)
Input clock
Output clock
(CKIO pin)
Internal clock Bus clock
Peripheral clock
2
H'1001
ON (×1)
ON (×4)
4:4:2
10 to 12.5
40 to 50
40 to 50
40 to 50
20 to 25
H'1002
ON (×1)
ON (×4)
4:4:4/3
10 to 12.5
40 to 50
40 to 50
40 to 50
13.33 to 16.66
H'1003
ON (×1)
ON (×4)
4:4:1
10 to 12.5
40 to 50
40 to 50
40 to 50
10 to 12.5
H'1103
ON (×2)
ON (×4)
8:4:2
10 to 12.5
40 to 50
80 to 100
40 to 50
20 to 25
H'1113
ON (×2)
ON (×4)
4:4:2
10 to 12.5
40 to 50
40 to 50
40 to 50
20 to 25
6
H'1000
ON (×1)
ON (×2)
2:2:2
10 to 16.66
20 to 33.33
20 to 33.33
20 to 33.33
20 to 33.33
H'1001
ON (×1)
ON (×2)
2:2:1
10 to 25
20 to 50
20 to 50
20 to 50
10 to 25
H'1002
ON (×1)
ON (×2)
2:2:2/3
10 to 25
20 to 50
20 to 50
20 to 50
6.66 to 16.66
H'1003
ON (×1)
ON (×2)
2:2:1/2
10 to 25
20 to 50
20 to 50
20 to 50
5 to 12.5
H'1101
ON (×2)
ON (×2)
4:2:2
10 to 16.66
20 to 33.33
40 to 66.66
20 to 33.33
20 to 33.33
H'1103
ON (×2)
ON (×2)
4:2:1
10 to 25
20 to 50
40 to 100
20 to 50
10 to 25
H'1111
ON (×2)
ON (×2)
2:2:2
10 to 16.66
20 to 33.33
20 to 33.33
20 to 33.33
20 to 33.33
H'1113
ON (×2)
ON (×2)
2:2:1
10 to 25
20 to 50
20 to 50
20 to 50
10 to 25
H'1202
ON (×3)
ON (×2)
6:2:2
13.33 to 16.66 26.66 to 33.33 80 to 100
26.66 to 33.33 26.66 to 33.33
H'1222
ON (×3)
ON (×2)
2:2:2
13.33 to 16.66 26.66 to 33.33 26.66 to 33.33 26.66 to 33.33 26.66 to 33.33