Renesas HD6417641 Manual De Usuario

Section 4   Clock Pulse Generator (CPG) 

 

 

Rev. 4.00  Sep. 14, 2005  Page 149 of 982 

 

 REJ09B0023-0400 

The CPG's control register is called the frequency control register (FRQCR). Refer the section 24, 
List of Registers, for the addresses of the registers and the state of each register in each processor 
state. 

The frequency control register (FRQCR) is a 16-bit readable/writable register used to specify 
whether a clock is output from the CKIO pin, the frequency multiplication ratio of PLL circuit 1, 
and the frequency division ratio of the internal clock and the peripheral clock. 

Only word access can be used on the FRQCR register. 

This register is initialized (to H'1003) only in the case of a power-on reset. This register retains its 
previous value after a manual reset or period in standby mode. The previous value is also retained 
when an internal reset is triggered by an overflow of the WDT. 

15 to 13 

 All 

0 

R 

Reserved 

These bits are always read as 0. The write value 
should always be 0. 

12 

CKOEN 

1 

R/W 

Clock Output Enable 

CKOEN specifies whether a clock is output from the 
CKIO and CKIO2 pins, or whether the CKIO and 
CKIO2 pins is placed in the level-fixed state during 
release of the standby mode (until the state enters 
STATUS1 = L and STATUS0 = L from an interrupt). If 
CKOEN is cleared to 0, the CKIO and CKIO2 pins are 
fixed at low during STATUS1 = L and STATUS0 = H. 
Therefore, the malfunction of an external circuit 
because of an unstable CKIO clock during release of 
the standby mode can be prevented. In clock 
operating mode 7, the CKIO pin functions as an input 
regardless of this bit value. 

0: The CKIO pin is fixed to the low level in the standby 

mode and while the system is leaving standby 
mode. 

1: Clock is output from CKIO pin (placed in the high-

impedance state during periods in standby mode).