Renesas HD6417641 Manual De Usuario
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Section 16 I
2
C Bus Interface 2 (IIC2)
Rev. 4.00 Sep. 14, 2005 Page 474 of 982
REJ09B0023-0400
SCL
ICCR1
Transfer clock
generation
circuit
Address
comparator
Interrupt
generator
Interrupt
request
Bus state
decision circuit
Arbitration
decision circuit
Noise canceler
Noise canceler
Output
control
control
Output
control
control
Transmission/
reception
control circuit
ICCR2
ICMR
ICSR
ICIER
ICDRR
ICDRS
ICDRT
I
2
C bus control register 1
I
2
C bus control register 2
I
2
C bus mode register
I
2
C bus status register
I
2
C bus interrupt enable register
I
2
C bus transmit data register
I
2
C bus receive data register
I
2
C bus shift register
Slave address register
NF2CYC register
NF2CYC register
[Legend]
ICCR1 :
ICCR2 :
ICMR :
ICSR :
ICIER :
ICDRT :
ICDRR :
ICDRS :
SAR :
NF2CYC:
ICCR2 :
ICMR :
ICSR :
ICIER :
ICDRT :
ICDRR :
ICDRS :
SAR :
NF2CYC:
SAR
SDA
Internal data bus
NF2CYC
Figure 16.1 Block Diagram of I
2
C Bus Interface 2