Renesas HD6417641 Manual De Usuario

Section 16   I

2

C Bus Interface 2 (IIC2) 

Rev. 4.00  Sep. 14, 2005  Page 476 of 982 

REJ09B0023-0400 

 

The I

2

C bus interface 2 has the following registers: 

•  I

2

C bus control register 1 (ICCR1) 

•  I

2

C bus control register 2 (ICCR2) 

•  I

2

C bus mode register (ICMR) 

•  I

2

C bus interrupt enable register (ICIER) 

•  I

2

C bus status register (ICSR) 

•  I

2

C bus slave address register (SAR) 

•  I

2

C bus transmit data register (ICDRT) 

•  I

2

C bus receive data register (ICDRR) 

•  I

2

C bus shift register (ICDRS) 

•  NF2CYC register (NF2CYC) 

 

ICCR1 is an 8-bit readable/writable register that enables or disables the I

2

C bus interface 2, 

controls transmission or reception, and selects master or slave mode, transmission or reception, 
and transfer clock frequency in master mode. 

ICCR1 is initialized to H'00 by a power-on reset. 

7 ICE  0 R/W 

I

2

C Bus Interface Enable 

0: This module is halted. (SCL and SDA pins are set to 

port function.) 

1: This bit is enabled for transfer operations. (SCL and 

SDA pins are bus drive state.) 

6 RCVD 

0 R/W 

Reception 

Disable 

This bit enables or disables the next operation when 
TRS is 0 and ICDRR is read. 

0: Enables next reception 

1: Disables next reception