Renesas 4513 Manual De Usuario

4513/4514 Group User’s Manual

2-9

Note when an I/O port except port P5 is used as an input port
Set the output latch to “1” and input the port value before input. If the output latch is set to “0,” “L”
level can be input.

Noise and latch-up prevention
Connect an approximate 0.1 

µ

F bypass capacitor directly to the V

SS

 line and the V

DD

 line with the

thickest possible wire at the shortest distance, and equalize its wiring in width and length.
The CNV

SS

 pin is also used as the V

PP

 pin (programming voltage = 12.5 V) at the built-in PROM

version.
Connect the CNV

SS

/V

PP

 pin to V

SS

 through an approximate 5 k

Ω

 resistor which is connected to the

CNV

SS

/V

PP

 pin at the shortest distance.

Note on multifunction
The input of D

6

, D

7

, P2

0

–P2

2

, CMP0-, CMP0+, CMP1-, CMP1+ and the input/output of P3

0

, P3

1

,

P4

0

–P4

3

 can be used even when CNTR0, CNTR1, S

CK

, S

OUT

, S

IN

, A

IN0

–A

IN3

, INT0, INT1, and A

IN4

–

A

IN7

 are selected.

Connection of unused pins
Table 2.1.6 shows the connections of unused pins.

SD, RD instructions
When the SD and RD instructions are used, do not set “1000

2

” or more to register Y.

Analog input pins
When both analog input A

IN4

–A

IN7

 and I/O port P4 function are used, note the following;

Even when register Q2 is used to set the pins for analog input, P4

0

/A

IN4

–P4

3

/A

IN7

 continue to

function as P4

0

–P4

3

 I/O. Accordingly, when any of them are used as I/O port P4 and others are

used as analog input pins, make sure to set the outputs of pins that are set for analog input to

“1.” Also, for the port input, the port input function of the pin functions as analog input is undefined.

Notes on port P3
In the 4513 Group, when the IAP3 instruction is executed, the contents of high-order 2 bits of register
A are undefined.