Renesas 4513 Manual De Usuario
APPLICATION
2.2 Interrupts
2-11
4513/4514 Group User’s Manual
2.2 Interrupts
The 4513/4514 Group has eight interrupt sources : external (INT0, INT1), timer 1, timer 2, timer 3, timer 4,
A-D, and serial I/O.
This section describes individual types of interrupts, related registers, application examples using interrupts
and notes.
A-D, and serial I/O.
This section describes individual types of interrupts, related registers, application examples using interrupts
and notes.
2.2.1 Interrupt functions
(1)
External 0 interrupt (INT0)
The interrupt request occurs by the change of input level of INT0 pin.
The interrupt valid waveform can be selected by the bits 1 and 2 of the interrupt control register I1.
The interrupt request occurs by the change of input level of INT0 pin.
The interrupt valid waveform can be selected by the bits 1 and 2 of the interrupt control register I1.
■
External 0 interrupt INT0 processing
●
When the interrupt is used
The interrupt occurrence is enabled when the bit 0 of the interrupt control register V1 and the
interrupt enable flag INTE are set to “1.” When the external 0 interrupt occurs, the interrupt
processing is executed from address 0 in page 1.
interrupt enable flag INTE are set to “1.” When the external 0 interrupt occurs, the interrupt
processing is executed from address 0 in page 1.
●
When the interrupt is not used
The interrupt is disabled and the SNZ0 instruction is valid when the bit 0 of register V1 is set
to “0.”
to “0.”
(2)
External 1 interrupt (INT1)
The interrupt request occurs by the change of input level of INT1 pin.
The interrupt valid waveform can be selected by the bits 1 and 2 of the interrupt control register I2.
The interrupt request occurs by the change of input level of INT1 pin.
The interrupt valid waveform can be selected by the bits 1 and 2 of the interrupt control register I2.
■
External 1 interrupt INT1 processing
●
When the interrupt is used
The interrupt occurrence is enabled when the bit 1 of the interrupt control register V1 and the
interrupt enable flag INTE are set to “1.” When the external 1 interrupt occurs, the interrupt
processing is executed from address 2 in page 1.
interrupt enable flag INTE are set to “1.” When the external 1 interrupt occurs, the interrupt
processing is executed from address 2 in page 1.
●
When the interrupt is not used
The interrupt is disabled and the SNZ1 instruction is valid when the bit 1 of register V1 is set
to “0.”
to “0.”
(3)
Timer 1 interrupt
The interrupt request occurs by the timer 1 underflow.
The interrupt request occurs by the timer 1 underflow.
■
Timer 1 interrupt processing
●
When the interrupt is used
The interrupt occurrence is enabled when the bit 2 of the interrupt control register V1 and the
interrupt enable flag INTE are set to “1.” When the timer 1 interrupt occurs, the interrupt processing
is executed from address 4 in page 1.
interrupt enable flag INTE are set to “1.” When the timer 1 interrupt occurs, the interrupt processing
is executed from address 4 in page 1.
●
When the interrupt is not used
The interrupt is disabled and the SNZT1 instruction is valid when the bit 2 of register V1 is set
to “0.”
to “0.”