HP (Hewlett-Packard) PCI-9111DG/HR Manual De Usuario
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Operation Theorem
refer to section 4.6 for timer/counter operation. This mode is ideal for high
speed A/D conversion. It can be combined with the FIFO half full interrupt
or EOC interrupt to transfer data. It is also possible to use software FIFO
polling to transfer data. The A/D trigger, A/D data transfer and Interrupt
can be set independently, most of the complex applications can thus be
covered.
speed A/D conversion. It can be combined with the FIFO half full interrupt
or EOC interrupt to transfer data. It is also possible to use software FIFO
polling to transfer data. The A/D trigger, A/D data transfer and Interrupt
can be set independently, most of the complex applications can thus be
covered.
It's recommend to use this mode if your applications need a fixed and
precise A/D sampling rate.
precise A/D sampling rate.
External Trigger (EITS=1, TPST=don‘t care)
Through the pin-16 of CN3 (ExtTrig), the A/D conversion also can be
triggered by an external signal. The A/D conversion starts as ExtTrig
changes from high to low. The conversion rate of this mode is more
flexible than the previous two modes, because the users can handle the
external signal by the outside device. The external trigger can be also
combined with the FIFO half interrupt, EOC interrupt or program FIFO
polling to transfer data.
triggered by an external signal. The A/D conversion starts as ExtTrig
changes from high to low. The conversion rate of this mode is more
flexible than the previous two modes, because the users can handle the
external signal by the outside device. The external trigger can be also
combined with the FIFO half interrupt, EOC interrupt or program FIFO
polling to transfer data.
4.1.4
A/D Data Transfer Modes
The A/D data are buffered in the FIFO memory. The FIFO size on
PCI-9111 is 1024 (1K) words. If the sampling rate is 100 KHz, the FIFO
can buffer 10.24 ms analog signal. After the FIFO is full, the lasting
coming data will be lost. The software must read out the FIFO data before
it becomes full.
PCI-9111 is 1024 (1K) words. If the sampling rate is 100 KHz, the FIFO
can buffer 10.24 ms analog signal. After the FIFO is full, the lasting
coming data will be lost. The software must read out the FIFO data before
it becomes full.
The data must be transferred to host memory after the date is ready and
before the FIFO is full. On the PCI-9111, many data transfer modes can
be used. The different transfer modes are specified as follows:
before the FIFO is full. On the PCI-9111, many data transfer modes can
be used. The different transfer modes are specified as follows:
Software Data Polling
The software data polling is the easiest way to transfer A/D data. This
mode can be used with software A/D trigger mode. After the A/D
conversion is triggered by software, the software should poll the FF_EF
bit of the A/D status register until it becomes low level.
mode can be used with software A/D trigger mode. After the A/D
conversion is triggered by software, the software should poll the FF_EF
bit of the A/D status register until it becomes low level.
If the FIFO is empty before the A/D start, the FF_EF bit will be low. After
the A/D is completed, the A/D data is written to FIFO immediately,
therefore the FF_EF becomes high. You can consider the FF_EF bit as
converted data ready status. That is, FF_EF is high means the data is
ready. Note that, while A/D is converted, the ADBUSY bit is low. After A/D
conversion, the ADBUSY become high to indicate not busy. Please do
NOT use this bit to poll the AD data.
the A/D is completed, the A/D data is written to FIFO immediately,
therefore the FF_EF becomes high. You can consider the FF_EF bit as
converted data ready status. That is, FF_EF is high means the data is
ready. Note that, while A/D is converted, the ADBUSY bit is low. After A/D
conversion, the ADBUSY become high to indicate not busy. Please do
NOT use this bit to poll the AD data.