IBM 150 Manual De Usuario
Hardware Overview
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are supported, namely the RISC System/6000, or the industry standard
OpenPIC.
OpenPIC.
Special attention was given to providing support for the memory controller
unit in the Model 260:
unit in the Model 260:
• Benchmark traces were used to fine-tune the buffer structure and queue
depths.
• The traces were also utilized to remove any wasted or unused cycles
internal to the memory controller.
The output from the memory controller function may be routed to main
memory, using the memory bus, or to I/O devices, using the I/O bus.
memory, using the memory bus, or to I/O devices, using the I/O bus.
To transport addressing information from the address controller to main
memory, the memory address bus is used. Data is passed from the data
controller to main memory using the memory data bus.This bus supports
sustainable memory bursts across a 128-bit data bus, which translates to a
read bandwidth of 1.6 GB/s at 100 MHz. The memory bus drives up to four
memory cards populated with non-buffered synchronous dynamic random
access memory (DRAM) standard dual in-line memory modules (DIMMs).
The SDRAM sizes supported are 16 MB, 64 MB, 128 MB, and 256 MB, with
64 MB being the minimum total system memory supported. Two error
checking and correction (ECC) codes are supported by this memory
controller unit. The first supports single bit correction, double bit detection,
and four bit packet detection. The second supports single bit correction, two
bit packet correction, and double packet detection.
memory, the memory address bus is used. Data is passed from the data
controller to main memory using the memory data bus.This bus supports
sustainable memory bursts across a 128-bit data bus, which translates to a
read bandwidth of 1.6 GB/s at 100 MHz. The memory bus drives up to four
memory cards populated with non-buffered synchronous dynamic random
access memory (DRAM) standard dual in-line memory modules (DIMMs).
The SDRAM sizes supported are 16 MB, 64 MB, 128 MB, and 256 MB, with
64 MB being the minimum total system memory supported. Two error
checking and correction (ECC) codes are supported by this memory
controller unit. The first supports single bit correction, double bit detection,
and four bit packet detection. The second supports single bit correction, two
bit packet correction, and double packet detection.
For access to I/O devices, the 6XX-MX I/O bridge bus is used. This bus is a
64-bit, time-multiplexed address and data bus, and can attach a variety of I/O
bridge chips. It runs asynchronously to the system and memory bus, and will
support speeds up to 75 MHz, translating to a sustainable read bandwidth of
533 MB/s. From the 6XX-MX bus, information passes through the PCI bridge
chip, where it is converted to PCI format for use with PCI devices. Each PCI
controller is able to communicate with a limited number of slots, so additional
PCI controllers are required to support a large number of PCI cards. Also,
specifications for 64-bit slots and standard 32-bit slots will often require
specialized PCI controllers.
64-bit, time-multiplexed address and data bus, and can attach a variety of I/O
bridge chips. It runs asynchronously to the system and memory bus, and will
support speeds up to 75 MHz, translating to a sustainable read bandwidth of
533 MB/s. From the 6XX-MX bus, information passes through the PCI bridge
chip, where it is converted to PCI format for use with PCI devices. Each PCI
controller is able to communicate with a limited number of slots, so additional
PCI controllers are required to support a large number of PCI cards. Also,
specifications for 64-bit slots and standard 32-bit slots will often require
specialized PCI controllers.
The ISA bridge located on the I/O backplane allows conversion from PCI to
ISA, enabling the use of native ISA devices. The integrated service
processor, also located on the I/O backplane, allows for improved reliability,
availability, and serviceability features.
ISA, enabling the use of native ISA devices. The integrated service
processor, also located on the I/O backplane, allows for improved reliability,
availability, and serviceability features.