IBM 150 Manual De Usuario
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RS/6000 43P 7043 Models 150 and 260 Handbook
2.3 Bus Architecture
The following sections cover the different bus architectures that exist on the
RS/6000 43P 7043 Models 150 and 260.
RS/6000 43P 7043 Models 150 and 260.
2.3.1 The PCI Bus Architecture
The Peripheral Component Interconnect (PCI) is a specification standard for
computer bus implementation developed by the PCI Special Interest Group
(PCI-SIG), led by a group of companies including Compaq, Digital, IBM, Intel,
and NCR. There are now over 300 companies in the PCI-SIG supporting the
architecture and currently producing PCI products.
computer bus implementation developed by the PCI Special Interest Group
(PCI-SIG), led by a group of companies including Compaq, Digital, IBM, Intel,
and NCR. There are now over 300 companies in the PCI-SIG supporting the
architecture and currently producing PCI products.
The goal is to provide a common system-board bus that could be used in
personal computers, from laptops to servers. It is envisioned as a local
system-board bus that would serve as a common design point, supporting
different system processors as the various processors evolve over time. This
is much like operating systems that have defined application binary interfaces
(ABIs) so that applications need not change with each generation of the
operating system. The PCI local bus would serve as a common hardware
interface that would not change with different versions of microprocessors.
personal computers, from laptops to servers. It is envisioned as a local
system-board bus that would serve as a common design point, supporting
different system processors as the various processors evolve over time. This
is much like operating systems that have defined application binary interfaces
(ABIs) so that applications need not change with each generation of the
operating system. The PCI local bus would serve as a common hardware
interface that would not change with different versions of microprocessors.
2.3.1.1 PCI Specification Revisions
According to PCI Specification Revision 2.0, the PCI bus operates on 32- or
64-bits of data at a clock speed of 33 MHz. However, as the speed of
processors continues to increase and devices such as video adapters require
more bandwidth, bus speeds must also increase to avoid data bottlenecks.
Consequently, PCI Specification Revision 2.0 has been superseded by PCI
Local Bus Specification Revision 2.1, which introduces support for a 66 MHz
bus operation speed, doubling the throughput of the former 33 MHz standard.
The RS/6000 43P Model 260 complies with PCI Local Bus Specification
Revision 2.1. IBM’s implementation of the 64-bit bus slot uses a clock speed
of 50 MHz. The Model 150 is PCI 2.0 compliant.
According to PCI Specification Revision 2.0, the PCI bus operates on 32- or
64-bits of data at a clock speed of 33 MHz. However, as the speed of
processors continues to increase and devices such as video adapters require
more bandwidth, bus speeds must also increase to avoid data bottlenecks.
Consequently, PCI Specification Revision 2.0 has been superseded by PCI
Local Bus Specification Revision 2.1, which introduces support for a 66 MHz
bus operation speed, doubling the throughput of the former 33 MHz standard.
The RS/6000 43P Model 260 complies with PCI Local Bus Specification
Revision 2.1. IBM’s implementation of the 64-bit bus slot uses a clock speed
of 50 MHz. The Model 150 is PCI 2.0 compliant.
Under PCI Specification Revision 2.1, the 66 MHz bus operation speed is an
optional feature and is backward-compatible with 33 MHz PCI devices and
buses. If a 66 MHz capable PCI device is installed in a 33 MHz PCI bus, the
device must operate at 33 MHz. Likewise, if any 33 MHz PCI devices are
installed into a 66 MHz PCI bus, the PCI bus must operate at 33 MHz.
optional feature and is backward-compatible with 33 MHz PCI devices and
buses. If a 66 MHz capable PCI device is installed in a 33 MHz PCI bus, the
device must operate at 33 MHz. Likewise, if any 33 MHz PCI devices are
installed into a 66 MHz PCI bus, the PCI bus must operate at 33 MHz.