Cypress CY7C68003 Manual De Usuario
Revised April 1, 2009
Page 5 of 5
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CY7C68003
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medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
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OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
The operation and configuration modes are described in
on page 4 and
Configuration Mode
on page 14
respectively. The ULPI Low power mode and Sleep mode are
described in the following sections:
described in the following sections:
ULPI Low Power Mode
In this mode, the link optionally places the TX2UL in low power
mode when the USB is suspended. TX2UL powers down all the
circuitry except for the interface pins and full speed receiver. To
enter low power mode, the link must set SuspendM in the
Function Control register to 0b. The TX2UL clock is stopped for
a minimum of five cycles after TX2UL accepts the register write.
To exit the low power mode, the link signals TX2UL to exit the
mode by asynchronously asserting a signal, STP. The TX2UL
wakes up its internal circuitry and when it meets the ULPI timing
requirements it deasserts DIR. The SuspendM register is set to
1b.
mode when the USB is suspended. TX2UL powers down all the
circuitry except for the interface pins and full speed receiver. To
enter low power mode, the link must set SuspendM in the
Function Control register to 0b. The TX2UL clock is stopped for
a minimum of five cycles after TX2UL accepts the register write.
To exit the low power mode, the link signals TX2UL to exit the
mode by asynchronously asserting a signal, STP. The TX2UL
wakes up its internal circuitry and when it meets the ULPI timing
requirements it deasserts DIR. The SuspendM register is set to
1b.
Sleep Mode
Sleep mode is entered by asserting RESET_N during the Normal
Operation Mode. When RESET_N is driven low for tSTATE (see
Operation Mode. When RESET_N is driven low for tSTATE (see
Table 21
on page 19 for tSTATE requirement) while CS_N is low,
TX2UL enters into Sleep Mode. VCC must remain supplied (ON)
during the sleep mode. This mode powers down all internal
circuitry except the RESET_N pin and the chip_config register.
The ULPI interface bus is tri-stated.
during the sleep mode. This mode powers down all internal
circuitry except the RESET_N pin and the chip_config register.
The ULPI interface bus is tri-stated.
During the Sleep Mode ensure that:
■
The ULPI interface IOs is either floating or driven high by the link
■
DP and DM are either floating or pull to 0V
■
Deassert RESET_N to exit the Sleep Mode.
VID and PID
The VID and PID are hard coded into Product ID and Vendor ID registers (read only) as shown in
.
Table 6. Immediate Register Values for VID and PID
Field Name
Size (bit)
Address (6 bits)
Value
Rd
Wr
Set
Clr
Vendor ID (VID) Low
8
00h
-
-
-
B4h
Vendor ID (VID) High
8
01h
-
-
-
04h
Product ID (PID) Low
8
02h
-
-
-
03h
Product ID (PID) High
8
03h
-
-
-
68h