Cypress CY7C1563V18 Manual De Usuario
CY7C1561V18, CY7C1576V18
CY7C1563V18, CY7C1565V18
CY7C1563V18, CY7C1565V18
Document Number: 001-05384 Rev. *F
Page 9 of 28
Depth Expansion
The CY7C1563V18 has a port select input for each port. This
enables for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed prior to the device being deselected.
enables for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed prior to the device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
on the SRAM and V
SS
to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5X the value of the
intended line impedance driven by the SRAM, the allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175
intended line impedance driven by the SRAM, the allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175
Ω and 350Ω
,
with V
DDQ
= 1.5V. The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR-II+ to simplify data capture
on high-speed systems. Two echo clocks are generated by the
QDR-II+. CQ is referenced with respect to K and CQ is refer-
enced with respect to K. These are free-running clocks and are
synchronized to the input clock of the QDR-II+. The timing for the
echo clocks are shown in
on high-speed systems. Two echo clocks are generated by the
QDR-II+. CQ is referenced with respect to K and CQ is refer-
enced with respect to K. These are free-running clocks and are
synchronized to the input clock of the QDR-II+. The timing for the
echo clocks are shown in
Valid Data Indicator (QVLD)
QVLD is provided on the QDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the QDR-II+ device
along with data output. This signal is also edge-aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
speed systems. The QVLD is generated by the QDR-II+ device
along with data output. This signal is also edge-aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
DLL
These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF pin. When the DLL is turned off, the device behaves in
QDR-I mode (with 1.0 cycle latency and a longer access time).
For more information, refer to the application note, “DLL Consid-
erations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be
reset by slowing or stopping the input clocks K and K for a
minimum of 30ns. However, it is not necessary to reset the DLL
to lock to the desired frequency. During Power up, when the
DOFF is tied HIGH, the DLL is locked after 2048 cycles of stable
clock.
function between 120 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF pin. When the DLL is turned off, the device behaves in
QDR-I mode (with 1.0 cycle latency and a longer access time).
For more information, refer to the application note, “DLL Consid-
erations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be
reset by slowing or stopping the input clocks K and K for a
minimum of 30ns. However, it is not necessary to reset the DLL
to lock to the desired frequency. During Power up, when the
DOFF is tied HIGH, the DLL is locked after 2048 cycles of stable
clock.
Application Example
shows four QDR-II+ used in an application.
Figure 1. Application Example
BUS MASTER
(CPU or ASIC)
DATA IN
DATA OUT
Address
Source K
Source K
Source K
Vt
Vt
Vt
R
R
CLKIN/CLKIN
D
A
A
K
SRAM #4
RQ = 250ohms
ZQ
CQ/CQ
Q
K
RPS WPS BWS
D
A
A
K
SRAM #1
RQ = 250ohms
ZQ
CQ/CQ
Q
K
RPS WPS BWS
RPS
WPS
BWS
BWS
R = 50ohms, Vt = V /2
DDQ
R